rename invert_a to invert_in because logical inverts RB
[soc.git] / src / soc / fu / alu / alu_input_record.py
1 from soc.fu.base_input_record import CompOpSubsetBase
2 from soc.decoder.power_enums import MicrOp, Function, CryIn
3 from nmigen.hdl.rec import Layout
4
5
6 class CompALUOpSubset(CompOpSubsetBase):
7 """CompALUOpSubset
8
9 a copy of the relevant subset information from Decode2Execute1Type
10 needed for ALU operations. use with eq_from_execute1 (below) to
11 grab subsets.
12 """
13 def __init__(self, name=None):
14 layout = (('insn_type', MicrOp),
15 ('fn_unit', Function),
16 ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
17 ('rc', Layout((("rc", 1), ("rc_ok", 1)))), # Data
18 ('oe', Layout((("oe", 1), ("oe_ok", 1)))), # Data
19 ('invert_in', 1),
20 ('zero_a', 1),
21 ('invert_out', 1),
22 ('write_cr0', 1),
23 ('input_carry', CryIn),
24 ('output_carry', 1),
25 ('is_32bit', 1),
26 ('is_signed', 1),
27 ('data_len', 4), # actually used by ALU, in OP_EXTS
28 ('insn', 32),
29 )
30 super().__init__(layout, name=name)
31