src/soc/fu/alu/alu_input_record.py

   1 from nmigen.hdl.rec import Record, Layout
   2
   3 from soc.decoder.power_enums import InternalOp, Function, CryIn
   4
   5
   6 class CompALUOpSubset(Record):
   7     """CompALUOpSubset
   8
   9     a copy of the relevant subset information from Decode2Execute1Type
  10     needed for ALU operations.  use with eq_from_execute1 (below) to
  11     grab subsets.
  12     """
  13     def __init__(self, name=None):
  14         layout = (('insn_type', InternalOp),
  15                   ('fn_unit', Function),
  16                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
  17                     #'cr = Signal(32, reset_less=True) # NO: this is from the CR SPR
  18                     #'xerc = XerBits() # NO: this is from the XER SPR
  19                   ('lk', 1),
  20                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
  21                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
  22                   ('invert_a', 1),
  23                   ('invert_out', 1),
  24                   ('input_carry', CryIn),
  25                   ('output_carry', 1),
  26                   ('input_cr', 1),
  27                   ('output_cr', 1),
  28                   ('is_32bit', 1),
  29                   ('is_signed', 1),
  30                   ('data_len', 4), # TODO: should be in separate CompLDSTSubset
  31                   ('insn', 32),
  32                   ('byte_reverse', 1),
  33                   ('sign_extend', 1))
  34
  35         Record.__init__(self, Layout(layout), name=name)
  36
  37         # grrr.  Record does not have kwargs
  38         self.insn_type.reset_less = True
  39         self.fn_unit.reset_less = True
  40         #self.cr = Signal(32, reset_less = True
  41         #self.xerc = XerBits(
  42         self.lk.reset_less = True
  43         self.invert_a.reset_less = True
  44         self.invert_out.reset_less = True
  45         self.input_carry.reset_less = True
  46         self.output_carry.reset_less = True
  47         self.input_cr.reset_less = True
  48         self.output_cr.reset_less = True
  49         self.is_32bit.reset_less = True
  50         self.is_signed.reset_less = True
  51         self.data_len.reset_less = True
  52         self.byte_reverse.reset_less = True
  53         self.sign_extend.reset_less = True
  54
  55     def eq_from_execute1(self, other):
  56         """ use this to copy in from Decode2Execute1Type
  57         """
  58         res = []
  59         for fname, sig in self.fields.items():
  60             eqfrom = other.fields[fname]
  61             res.append(sig.eq(eqfrom))
  62         return res
  63
  64     def ports(self):
  65         return [self.insn_type,
  66                 #self.cr,
  67                 #self.xerc,
  68                 self.lk,
  69                 self.invert_a,
  70                 self.invert_out,
  71                 self.input_carry,
  72                 self.output_carry,
  73                 self.input_cr,
  74                 self.output_cr,
  75                 self.is_32bit,
  76                 self.is_signed,
  77                 self.data_len,
  78                 self.byte_reverse,
  79                 self.sign_extend,
  80         ]