1 # Proof of correctness for partitioned equal signal combiner
2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
4 from nmigen
import (Module
, Signal
, Elaboratable
, Mux
, Cat
, Repl
,
6 from nmigen
.asserts
import Assert
, AnyConst
, Assume
, Cover
7 from nmigen
.test
.utils
import FHDLTestCase
8 from nmigen
.cli
import rtlil
10 from soc
.fu
.alu
.main_stage
import ALUMainStage
11 from soc
.fu
.alu
.pipe_data
import ALUPipeSpec
12 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
13 from soc
.decoder
.power_enums
import InternalOp
17 # This defines a module to drive the device under test and assert
18 # properties about its outputs
19 class Driver(Elaboratable
):
24 def elaborate(self
, platform
):
28 rec
= CompALUOpSubset()
29 # Setup random inputs for dut.op
32 comb
+= p
.eq(AnyConst(width
))
34 pspec
= ALUPipeSpec(id_wid
=2)
35 m
.submodules
.dut
= dut
= ALUMainStage(pspec
)
37 # convenience variables
40 ca_in
= dut
.i
.xer_ca
[0] # CA carry in
41 ca32_in
= dut
.i
.xer_ca
[1] # CA32 carry in 32
42 so_in
= dut
.i
.xer_so
# SO sticky overflow
44 ca_o
= dut
.o
.xer_ca
.data
[0] # CA carry out
45 ca32_o
= dut
.o
.xer_ca
.data
[1] # CA32 carry out32
46 ov_o
= dut
.o
.xer_ov
.data
[0] # OV overflow
47 ov32_o
= dut
.o
.xer_ov
.data
[1] # OV32 overflow32
51 comb
+= [a
.eq(AnyConst(64)),
53 ca_in
.eq(AnyConst(0b11)),
54 so_in
.eq(AnyConst(1))]
56 comb
+= dut
.i
.ctx
.op
.eq(rec
)
58 # Assert that op gets copied from the input to output
59 for rec_sig
in rec
.ports():
61 dut_sig
= getattr(dut
.o
.ctx
.op
, name
)
62 comb
+= Assert(dut_sig
== rec_sig
)
64 # signed and signed/32 versions of input a
65 a_signed
= Signal(signed(64))
66 a_signed_32
= Signal(signed(32))
67 comb
+= a_signed
.eq(a
)
68 comb
+= a_signed_32
.eq(a
[0:32])
70 with m
.If(rec
.is_32bit
):
71 comb
+= Assume(a
[32:64] == 0)
72 comb
+= Assume(b
[32:64] == 0)
75 comb
+= o_ok
.eq(1) # will be set to zero if no op takes place
77 # main assertion of arithmetic operations
78 with m
.Switch(rec
.insn_type
):
79 with m
.Case(InternalOp
.OP_ADD
):
81 comb
+= Assert(Cat(o
, ca_o
) == (a
+ b
+ ca_in
))
83 # CA32 - XXX note this fails! replace with ca_in and it works
84 comb
+= Assert((a
[0:32] + b
[0:32] + ca_in
)[32] == ca32_o
)
86 # From microwatt execute1.vhdl line 130
87 comb
+= Assert(ov_o
== ((ca_o ^ o
[-1]) & ~
(a
[-1] ^ b
[-1])))
88 comb
+= Assert(ov32_o
== ((ca32_o ^ o
[31]) & ~
(a
[31] ^ b
[31])))
90 with m
.Case(InternalOp
.OP_EXTS
):
92 with m
.If(rec
.data_len
== i
):
93 comb
+= Assert(o
[0:i
*8] == a
[0:i
*8])
94 comb
+= Assert(o
[i
*8:64] == Repl(a
[i
*8-1], 64-(i
*8)))
96 with m
.Case(InternalOp
.OP_CMP
):
97 # CMP is defined as not taking in carry
98 comb
+= Assume(ca_in
== 0)
99 comb
+= Assert(o
== (a
+b
)[0:64])
101 with m
.Case(InternalOp
.OP_CMPEQB
):
105 comb
+= eqs
[i
].eq(src1
== b
[i
*8:(i
+1)*8])
106 comb
+= Assert(dut
.o
.cr0
[2] == eqs
.any())
111 # check that data ok was only enabled when op actioned
112 comb
+= Assert(dut
.o
.o
.ok
== o_ok
)
117 class ALUTestCase(FHDLTestCase
):
118 def test_formal(self
):
120 self
.assertFormal(module
, mode
="bmc", depth
=2)
121 self
.assertFormal(module
, mode
="cover", depth
=2)
122 def test_ilang(self
):
124 vl
= rtlil
.convert(dut
, ports
=[])
125 with
open("alu_main_stage.il", "w") as f
:
129 if __name__
== '__main__':