src/soc/fu/alu/input_stage.py

   1 # This stage is intended to adjust the input data before sending it to
   2 # the acutal ALU. Things like handling inverting the input, carry_in
   3 # generation for subtraction, and handling of immediates should happen
   4 # here
   5 from nmigen import (Module, Signal, Cat, Const, Mux, Repl, signed,
   6                     unsigned)
   7 from nmutil.pipemodbase import PipeModBase
   8 from soc.decoder.power_enums import InternalOp
   9 from soc.fu.alu.pipe_data import ALUInputData
  10 from soc.decoder.power_enums import CryIn
  11
  12
  13 class ALUInputStage(PipeModBase):
  14     def __init__(self, pspec):
  15         super().__init__(pspec, "input")
  16
  17     def ispec(self):
  18         return ALUInputData(self.pspec)
  19
  20     def ospec(self):
  21         return ALUInputData(self.pspec)
  22
  23     def elaborate(self, platform):
  24         m = Module()
  25         comb = m.d.comb
  26         ctx = self.i.ctx
  27
  28         ##### operand A #####
  29
  30         # operand a to be as-is or inverted
  31         a = Signal.like(self.i.a)
  32
  33         with m.If(ctx.op.invert_a):
  34             comb += a.eq(~self.i.a)
  35         with m.Else():
  36             comb += a.eq(self.i.a)
  37
  38         comb += self.o.a.eq(a)
  39         comb += self.o.b.eq(self.i.b)
  40
  41         ##### carry-in #####
  42
  43         # either copy incoming carry or set to 1/0 as defined by op
  44         with m.Switch(ctx.op.input_carry):
  45             with m.Case(CryIn.ZERO):
  46                 comb += self.o.carry_in.eq(0)
  47             with m.Case(CryIn.ONE):
  48                 comb += self.o.carry_in.eq(1)
  49             with m.Case(CryIn.CA):
  50                 comb += self.o.carry_in.eq(self.i.carry_in)
  51
  52         ##### sticky overflow and context (both pass-through) #####
  53
  54         comb += self.o.so.eq(self.i.so)
  55         comb += self.o.ctx.eq(ctx)
  56
  57         return m