src/soc/fu/alu/main_stage.py

   1 # This stage is intended to do most of the work of executing the Arithmetic
   2 # instructions. This would be like the additions, compares, and sign-extension
   3 # as well as carry and overflow generation. This module
   4 # however should not gate the carry or overflow, that's up to the
   5 # output stage
   6 from nmigen import (Module, Signal, Cat, Repl, Mux, Const)
   7 from nmutil.pipemodbase import PipeModBase
   8 from nmutil.extend import exts
   9 from soc.fu.alu.pipe_data import ALUInputData, ALUOutputData
  10 from ieee754.part.partsig import PartitionedSignal
  11 from soc.decoder.power_enums import InternalOp
  12
  13
  14 class ALUMainStage(PipeModBase):
  15     def __init__(self, pspec):
  16         super().__init__(pspec, "main")
  17
  18     def ispec(self):
  19         return ALUInputData(self.pspec)
  20
  21     def ospec(self):
  22         return ALUOutputData(self.pspec) # TODO: ALUIntermediateData
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26         comb = m.d.comb
  27         cry_o, o, cr0 = self.o.xer_ca, self.o.o, self.o.cr0
  28         ov_o = self.o.xer_ov
  29         a, b, cry_i, op = self.i.a, self.i.b, self.i.xer_ca, self.i.ctx.op
  30
  31         # check if op is 32-bit, and get sign bit from operand a
  32         is_32bit = Signal(reset_less=True)
  33         sign_bit = Signal(reset_less=True)
  34         comb += is_32bit.eq(op.is_32bit)
  35         comb += sign_bit.eq(Mux(is_32bit, a[31], a[63]))
  36
  37         # little trick: do the add using only one add (not 2)
  38         # LSB: carry-in [0].  op/result: [1:-1].  MSB: carry-out [-1]
  39         add_a = Signal(a.width + 2, reset_less=True)
  40         add_b = Signal(a.width + 2, reset_less=True)
  41         add_o = Signal(a.width + 2, reset_less=True)
  42         with m.If((op.insn_type == InternalOp.OP_ADD) |
  43                   (op.insn_type == InternalOp.OP_CMP)):
  44             # in bit 0, 1+carry_in creates carry into bit 1 and above
  45             comb += add_a.eq(Cat(cry_i[0], a, Const(0, 1)))
  46             comb += add_b.eq(Cat(Const(1, 1), b, Const(0, 1)))
  47             comb += add_o.eq(add_a + add_b)
  48
  49         ##########################
  50         # main switch-statement for handling arithmetic operations
  51
  52         with m.Switch(op.insn_type):
  53             #### CMP, CMPL ####
  54             with m.Case(InternalOp.OP_CMP):
  55                 # this is supposed to be inverted (b-a, not a-b)
  56                 # however we have a trick: instead of adding either 2x 64-bit
  57                 # MUXes to invert a and b, or messing with a 64-bit output,
  58                 # swap +ve and -ve test in the *output* stage using an XOR gate
  59                 comb += o.eq(add_o[1:-1])
  60
  61             #### add ####
  62             with m.Case(InternalOp.OP_ADD):
  63                 # bit 0 is not part of the result, top bit is the carry-out
  64                 comb += o.eq(add_o[1:-1])
  65
  66                 # see microwatt OP_ADD code
  67                 # https://bugs.libre-soc.org/show_bug.cgi?id=319#c5
  68                 comb += cry_o.data[0].eq(add_o[-1]) # XER.CO
  69                 comb += cry_o.data[1].eq(add_o[33] ^ (a[32] ^ b[32])) # XER.CO32
  70                 comb += ov_o.data[0].eq((add_o[-2] != a[-1]) & (a[-1] == b[-1]))
  71                 comb += ov_o.data[1].eq((add_o[32] != a[31]) & (a[31] == b[31]))
  72
  73             #### exts (sign-extend) ####
  74             with m.Case(InternalOp.OP_EXTS):
  75                 with m.If(op.data_len == 1):
  76                     comb += o.eq(exts(a, 8, 64))
  77                 with m.If(op.data_len == 2):
  78                     comb += o.eq(exts(a, 16, 64))
  79                 with m.If(op.data_len == 4):
  80                     comb += o.eq(exts(a, 32, 64))
  81
  82             #### cmpeqb ####
  83             with m.Case(InternalOp.OP_CMPEQB):
  84                 eqs = Signal(8, reset_less=True)
  85                 src1 = Signal(8, reset_less=True)
  86                 comb += src1.eq(a[0:8])
  87                 for i in range(8):
  88                     comb += eqs[i].eq(src1 == b[8*i:8*(i+1)])
  89                 comb += cr0.data.eq(Cat(Const(0, 2), eqs.any(), Const(0, 1)))
  90
  91         ###### sticky overflow and context, both pass-through #####
  92
  93         comb += self.o.xer_so.data.eq(self.i.xer_so)
  94         comb += self.o.ctx.eq(self.i.ctx)
  95
  96         return m