src/soc/fu/alu/pipe_data.py

   1 from nmigen import Signal, Const
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from soc.fu.alu.alu_input_record import CompALUOpSubset
   4 from ieee754.fpcommon.getop import FPPipeContext
   5 from soc.decoder.power_decoder2 import Data
   6
   7 class IntegerData:
   8
   9     def __init__(self, pspec):
  10         self.ctx = FPPipeContext(pspec)
  11         self.muxid = self.ctx.muxid
  12
  13     def __iter__(self):
  14         yield from self.ctx
  15
  16     def eq(self, i):
  17         return [self.ctx.eq(i.ctx)]
  18
  19     def ports(self):
  20         return self.ctx.ports()
  21
  22
  23 class ALUInputData(IntegerData):
  24     def __init__(self, pspec):
  25         super().__init__(pspec)
  26         self.a = Signal(64, reset_less=True) # RA
  27         self.b = Signal(64, reset_less=True) # RB/immediate
  28         self.xer_so = Signal(reset_less=True) # XER bit 32: SO
  29         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  30
  31     def __iter__(self):
  32         yield from super().__iter__()
  33         yield self.a
  34         yield self.b
  35         yield self.xer_ca
  36         yield self.xer_so
  37
  38     def eq(self, i):
  39         lst = super().eq(i)
  40         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  41                       self.xer_ca.eq(i.xer_ca),
  42                       self.xer_so.eq(i.xer_so)]
  43
  44 # TODO: ALUIntermediateData which does not have
  45 # cr0, ov, ov32 in it (because they are generated as outputs by
  46 # the final output stage, not by the intermediate stage)
  47 # https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
  48
  49 class ALUOutputData(IntegerData):
  50     def __init__(self, pspec):
  51         super().__init__(pspec)
  52         self.o = Signal(64, reset_less=True, name="stage_o")
  53         self.cr0 = Data(4, name="cr0")
  54         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
  55         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
  56         self.xer_so = Data(1, name="xer_so")
  57
  58     def __iter__(self):
  59         yield from super().__iter__()
  60         yield self.o
  61         yield self.xer_ca
  62         yield self.cr0
  63         yield self.xer_ov
  64         yield self.xer_so
  65
  66     def eq(self, i):
  67         lst = super().eq(i)
  68         return lst + [self.o.eq(i.o),
  69                       self.xer_ca.eq(i.xer_ca),
  70                       self.cr0.eq(i.cr0),
  71                       self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
  72
  73
  74 class IntPipeSpec:
  75     def __init__(self, id_wid=2, op_wid=1):
  76         self.id_wid = id_wid
  77         self.op_wid = op_wid
  78         self.opkls = lambda _: CompALUOpSubset(name="op")
  79         self.stage = None
  80
  81
  82 class ALUPipeSpec(IntPipeSpec):
  83     def __init__(self, id_wid, op_wid):
  84         super().__init__(id_wid, op_wid)
  85         self.pipekls = SimpleHandshakeRedir