src/soc/fu/alu/pipe_data.py

   1 from nmigen import Signal, Const
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from soc.fu.alu.alu_input_record import CompALUOpSubset
   4 from ieee754.fpcommon.getop import FPPipeContext
   5 from soc.decoder.power_decoder2 import Data
   6
   7
   8 class IntegerData:
   9
  10     def __init__(self, pspec):
  11         self.ctx = FPPipeContext(pspec)
  12         self.muxid = self.ctx.muxid
  13
  14     def __iter__(self):
  15         yield from self.ctx
  16
  17     def eq(self, i):
  18         return [self.ctx.eq(i.ctx)]
  19
  20     def ports(self):
  21         return self.ctx.ports()
  22
  23
  24 class ALUInputData(IntegerData):
  25     regspec = [('INT', 'a', '0:63'),
  26                ('INT', 'b', '0:63'),
  27                ('XER', 'xer_so', '32'),
  28                ('XER', 'xer_ca', '34,45')]
  29     def __init__(self, pspec):
  30         super().__init__(pspec)
  31         self.a = Signal(64, reset_less=True) # RA
  32         self.b = Signal(64, reset_less=True) # RB/immediate
  33         self.xer_so = Signal(reset_less=True) # XER bit 32: SO
  34         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  35
  36     def __iter__(self):
  37         yield from super().__iter__()
  38         yield self.a
  39         yield self.b
  40         yield self.xer_ca
  41         yield self.xer_so
  42
  43     def eq(self, i):
  44         lst = super().eq(i)
  45         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  46                       self.xer_ca.eq(i.xer_ca),
  47                       self.xer_so.eq(i.xer_so)]
  48
  49
  50 class ALUOutputData(IntegerData):
  51     regspec = [('INT', 'o', '0:63'),
  52                ('CR', 'cr0', '0:3'),
  53                ('XER', 'xer_ca', '34,45'),
  54                ('XER', 'xer_ov', '33,44'),
  55                ('XER', 'xer_so', '32')]
  56     def __init__(self, pspec):
  57         super().__init__(pspec)
  58         self.o = Signal(64, reset_less=True, name="stage_o")
  59         self.cr0 = Data(4, name="cr0")
  60         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
  61         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
  62         self.xer_so = Data(1, name="xer_so")
  63
  64     def __iter__(self):
  65         yield from super().__iter__()
  66         yield self.o
  67         yield self.xer_ca
  68         yield self.cr0
  69         yield self.xer_ov
  70         yield self.xer_so
  71
  72     def eq(self, i):
  73         lst = super().eq(i)
  74         return lst + [self.o.eq(i.o),
  75                       self.xer_ca.eq(i.xer_ca),
  76                       self.cr0.eq(i.cr0),
  77                       self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
  78
  79
  80 class ALUPipeSpec:
  81     regspec = (ALUInputData.regspec, ALUOutputData.regspec)
  82     opsubsetkls = CompALUOpSubset
  83     def __init__(self, id_wid, op_wid):
  84         self.pipekls = SimpleHandshakeRedir
  85         self.id_wid = id_wid
  86         self.op_wid = op_wid
  87         self.opkls = lambda _: self.opsubsetkls(name="op")
  88         self.stage = None