src/soc/fu/alu/pipe_data.py

   1 from nmigen import Signal, Const
   2 from nmutil.dynamicpipe import SimpleHandshakeRedir
   3 from soc.fu.alu.alu_input_record import CompALUOpSubset
   4 from ieee754.fpcommon.getop import FPPipeContext
   5 from soc.decoder.power_decoder2 import Data
   6
   7 class IntegerData:
   8
   9     def __init__(self, pspec):
  10         self.ctx = FPPipeContext(pspec)
  11         self.muxid = self.ctx.muxid
  12
  13     def __iter__(self):
  14         yield from self.ctx
  15
  16     def eq(self, i):
  17         return [self.ctx.eq(i.ctx)]
  18
  19     def ports(self):
  20         return self.ctx.ports()
  21
  22
  23 class ALUInputData(IntegerData):
  24     regspec = [('INT', 'a', '0:63'),
  25                ('INT', 'b', '0:63'),
  26                ('XER', 'xer_so', '32'),
  27                ('XER', 'xer_ca', '34,45')]
  28     def __init__(self, pspec):
  29         super().__init__(pspec)
  30         self.a = Signal(64, reset_less=True) # RA
  31         self.b = Signal(64, reset_less=True) # RB/immediate
  32         self.xer_so = Signal(reset_less=True) # XER bit 32: SO
  33         self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
  34
  35     def __iter__(self):
  36         yield from super().__iter__()
  37         yield self.a
  38         yield self.b
  39         yield self.xer_ca
  40         yield self.xer_so
  41
  42     def eq(self, i):
  43         lst = super().eq(i)
  44         return lst + [self.a.eq(i.a), self.b.eq(i.b),
  45                       self.xer_ca.eq(i.xer_ca),
  46                       self.xer_so.eq(i.xer_so)]
  47
  48 # TODO: ALUIntermediateData which does not have
  49 # cr0, ov, ov32 in it (because they are generated as outputs by
  50 # the final output stage, not by the intermediate stage)
  51 # https://bugs.libre-soc.org/show_bug.cgi?id=305#c19
  52
  53 class ALUOutputData(IntegerData):
  54     regspec = [('INT', 'o', '0:63'),
  55                ('CR', 'cr0', '0:3'),
  56                ('XER', 'xer_ca', '34,45'),
  57                ('XER', 'xer_ov', '33,44'),
  58                ('XER', 'xer_so', '32')]
  59     def __init__(self, pspec):
  60         super().__init__(pspec)
  61         self.o = Signal(64, reset_less=True, name="stage_o")
  62         self.cr0 = Data(4, name="cr0")
  63         self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
  64         self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
  65         self.xer_so = Data(1, name="xer_so")
  66
  67     def __iter__(self):
  68         yield from super().__iter__()
  69         yield self.o
  70         yield self.xer_ca
  71         yield self.cr0
  72         yield self.xer_ov
  73         yield self.xer_so
  74
  75     def eq(self, i):
  76         lst = super().eq(i)
  77         return lst + [self.o.eq(i.o),
  78                       self.xer_ca.eq(i.xer_ca),
  79                       self.cr0.eq(i.cr0),
  80                       self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
  81
  82
  83 class IntPipeSpec:
  84     def __init__(self, id_wid=2, op_wid=1):
  85         self.id_wid = id_wid
  86         self.op_wid = op_wid
  87         self.opkls = lambda _: CompALUOpSubset(name="op")
  88         self.stage = None
  89
  90
  91 class ALUPipeSpec(IntPipeSpec):
  92     def __init__(self, id_wid, op_wid):
  93         super().__init__(id_wid, op_wid)
  94         self.pipekls = SimpleHandshakeRedir