42bea516e49d7967026e6dd08ed23d5a7b302116
1 from nmigen
import Signal
, Const
2 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
3 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
4 from ieee754
.fpcommon
.getop
import FPPipeContext
5 from soc
.decoder
.power_decoder2
import Data
8 class ALUInputData(IntegerData
):
9 regspec
= [('INT', 'a', '0:63'),
11 ('XER', 'xer_so', '32'),
12 ('XER', 'xer_ca', '34,45')]
13 def __init__(self
, pspec
):
14 super().__init
__(pspec
)
15 self
.a
= Signal(64, reset_less
=True) # RA
16 self
.b
= Signal(64, reset_less
=True) # RB/immediate
17 self
.xer_so
= Signal(reset_less
=True) # XER bit 32: SO
18 self
.xer_ca
= Signal(2, reset_less
=True) # XER bit 34/45: CA/CA32
21 yield from super().__iter
__()
29 return lst
+ [self
.a
.eq(i
.a
), self
.b
.eq(i
.b
),
30 self
.xer_ca
.eq(i
.xer_ca
),
31 self
.xer_so
.eq(i
.xer_so
)]
34 class ALUOutputData(IntegerData
):
35 regspec
= [('INT', 'o', '0:63'),
37 ('XER', 'xer_ca', '34,45'),
38 ('XER', 'xer_ov', '33,44'),
39 ('XER', 'xer_so', '32')]
40 def __init__(self
, pspec
):
41 super().__init
__(pspec
)
42 self
.o
= Signal(64, reset_less
=True, name
="stage_o")
43 self
.cr0
= Data(4, name
="cr0")
44 self
.xer_ca
= Data(2, name
="xer_co") # bit0: ca, bit1: ca32
45 self
.xer_ov
= Data(2, name
="xer_ov") # bit0: ov, bit1: ov32
46 self
.xer_so
= Data(1, name
="xer_so")
49 yield from super().__iter
__()
58 return lst
+ [self
.o
.eq(i
.o
),
59 self
.xer_ca
.eq(i
.xer_ca
),
61 self
.xer_ov
.eq(i
.xer_ov
), self
.xer_so
.eq(i
.xer_so
)]
64 class ALUPipeSpec(CommonPipeSpec
):
65 regspec
= (ALUInputData
.regspec
, ALUOutputData
.regspec
)
66 opsubsetkls
= CompALUOpSubset