src/soc/fu/alu/pipe_data.py

   1 from soc.fu.alu.alu_input_record import CompALUOpSubset
   2 from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
   3
   4
   5 class ALUInputData(FUBaseData):
   6     def __init__(self, pspec):
   7         super().__init__(pspec, False)
   8         # convenience
   9         self.a, self.b = self.ra, self.rb
  10
  11     @property
  12     def regspec(self):
  13         return [('INT', 'ra', self.intrange),  # RA
  14                ('INT', 'rb', self.intrange),  # RB/immediate
  15                ('XER', 'xer_so', '32'),  # XER bit 32: SO
  16                ('XER', 'xer_ca', '34,45')]  # XER bit 34/45: CA/CA32
  17
  18
  19
  20 class ALUOutputData(FUBaseData):
  21     def __init__(self, pspec):
  22         super().__init__(pspec, True)
  23         # convenience
  24         self.cr0 = self.cr_a
  25
  26     @property
  27     def regspec(self):
  28         return [('INT', 'o', self.intrange),
  29                ('CR', 'cr_a', '0:3'),
  30                ('XER', 'xer_ca', '34,45'),  # bit0: ca, bit1: ca32
  31                ('XER', 'xer_ov', '33,44'),  # bit0: ov, bit1: ov32
  32                ('XER', 'xer_so', '32')]
  33
  34
  35
  36 class ALUPipeSpec(CommonPipeSpec):
  37     opsubsetkls = CompALUOpSubset
  38     regspecklses = (ALUInputData, ALUOutputData)