Merge branch 'master' of ssh://git.libre-riscv.org:922/soc
[soc.git] / src / soc / fu / alu / pipe_data.py
1 from nmigen import Signal, Const, Cat
2 from soc.fu.alu.alu_input_record import CompALUOpSubset
3 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
4 from ieee754.fpcommon.getop import FPPipeContext
5 from soc.decoder.power_decoder2 import Data
6
7
8 class ALUInputData(IntegerData):
9 regspec = [('INT', 'ra', '0:63'),
10 ('INT', 'rb', '0:63'),
11 ('XER', 'xer_so', '32'),
12 ('XER', 'xer_ca', '34,45')]
13 def __init__(self, pspec):
14 super().__init__(pspec)
15 self.ra = Signal(64, reset_less=True) # RA
16 self.rb = Signal(64, reset_less=True) # RB/immediate
17 self.xer_so = Signal(reset_less=True) # XER bit 32: SO
18 self.xer_ca = Signal(2, reset_less=True) # XER bit 34/45: CA/CA32
19 # convenience
20 self.a, self.b = self.ra, self.rb
21
22 def __iter__(self):
23 yield from super().__iter__()
24 yield self.ra
25 yield self.rb
26 yield self.xer_ca
27 yield self.xer_so
28
29 def eq(self, i):
30 lst = super().eq(i)
31 return lst + [self.ra.eq(i.ra), self.rb.eq(i.rb),
32 self.xer_ca.eq(i.xer_ca),
33 self.xer_so.eq(i.xer_so)]
34
35
36 class ALUOutputData(IntegerData):
37 regspec = [('INT', 'o', '0:63'),
38 ('CR', 'cr_a', '0:3'),
39 ('XER', 'xer_ca', '34,45'),
40 ('XER', 'xer_ov', '33,44'),
41 ('XER', 'xer_so', '32')]
42 def __init__(self, pspec):
43 super().__init__(pspec)
44 self.o = Data(64, name="stage_o")
45 self.cr_a = Data(4, name="cr_a")
46 self.xer_ca = Data(2, name="xer_co") # bit0: ca, bit1: ca32
47 self.xer_ov = Data(2, name="xer_ov") # bit0: ov, bit1: ov32
48 self.xer_so = Data(1, name="xer_so")
49 # convenience
50 self.cr0 = self.cr_a
51
52 def __iter__(self):
53 yield from super().__iter__()
54 yield self.o
55 yield self.xer_ca
56 yield self.cr_a
57 yield self.xer_ov
58 yield self.xer_so
59
60 def eq(self, i):
61 lst = super().eq(i)
62 return lst + [self.o.eq(i.o),
63 self.xer_ca.eq(i.xer_ca),
64 self.cr_a.eq(i.cr_a),
65 self.xer_ov.eq(i.xer_ov), self.xer_so.eq(i.xer_so)]
66
67
68 class ALUPipeSpec(CommonPipeSpec):
69 regspec = (ALUInputData.regspec, ALUOutputData.regspec)
70 opsubsetkls = CompALUOpSubset