c8e985247d4dfd9e6366662bdedc8ee69f020e58
1 from soc
.fu
.test
.common
import TestAccumulatorBase
2 from soc
.config
.endian
import bigendian
3 from soc
.simulator
.program
import Program
4 from soc
.decoder
.isa
.caller
import SVP64State
5 from soc
.sv
.trans
.svp64
import SVP64Asm
8 class SVP64ALUTestCase(TestAccumulatorBase
):
10 def case_1_sv_add(self
):
12 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
13 # 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
14 isa
= SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
17 initial_regs
= [0] * 32
18 initial_regs
[9] = 0x1234
19 initial_regs
[10] = 0x1111
20 initial_regs
[5] = 0x4321
21 initial_regs
[6] = 0x2223
22 svstate
= SVP64State()
23 svstate
.vl
[0:7] = 2 # VL
24 svstate
.maxvl
[0:7] = 2 # MAXVL
25 print("SVSTATE", bin(svstate
.spr
.asint()))
27 self
.add_case(Program(lst
, bigendian
), initial_regs
,
28 initial_svstate
=svstate
)