1 from soc
.fu
.test
.common
import (TestAccumulatorBase
, skip_case
)
2 from soc
.config
.endian
import bigendian
3 from soc
.simulator
.program
import Program
4 from soc
.decoder
.isa
.caller
import SVP64State
5 from soc
.sv
.trans
.svp64
import SVP64Asm
8 class SVP64ALUTestCase(TestAccumulatorBase
):
10 @skip_case("VL hardware loop is not yet implemented")
11 def case_1_sv_add(self
):
13 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
14 # 2 = 6 + 10 => 0x3334 = 0x2223 + 0x1111
15 isa
= SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
19 # initial values in GPR regfile
20 initial_regs
= [0] * 32
21 initial_regs
[9] = 0x1234
22 initial_regs
[10] = 0x1111
23 initial_regs
[5] = 0x4321
24 initial_regs
[6] = 0x2223
25 # SVSTATE (in this case, VL=2)
26 svstate
= SVP64State()
27 svstate
.vl
[0:7] = 2 # VL
28 svstate
.maxvl
[0:7] = 2 # MAXVL
29 print("SVSTATE", bin(svstate
.spr
.asint()))
31 self
.add_case(Program(lst
, bigendian
), initial_regs
,
32 initial_svstate
=svstate
)
34 def case_2_sv_add_scalar(self
):
36 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
37 isa
= SVP64Asm(['sv.add 1, 5, 9'])
41 # initial values in GPR regfile
42 initial_regs
= [0] * 32
43 initial_regs
[9] = 0x1234
44 initial_regs
[5] = 0x4321
45 svstate
= SVP64State()
46 # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
47 svstate
.vl
[0:7] = 1 # VL
48 svstate
.maxvl
[0:7] = 1 # MAXVL
49 print("SVSTATE", bin(svstate
.spr
.asint()))
51 self
.add_case(Program(lst
, bigendian
), initial_regs
,
52 initial_svstate
=svstate
)
54 # This case helps checking the encoding of the Extra field
55 # It was built so the v3.0b registers are: 3, 2, 1
56 # and the Extra field is: 101.110.111
57 # The expected SVP64 register numbers are: 13, 10, 7
58 # Any mistake in decoding will probably give a different answer
59 def case_3_sv_check_extra(self
):
61 # 13 = 10 + 7 => 0x4242 = 0x1230 + 0x3012
62 isa
= SVP64Asm(['sv.add 13.v, 10.v, 7.v'])
66 # initial values in GPR regfile
67 initial_regs
= [0] * 32
68 initial_regs
[7] = 0x3012
69 initial_regs
[10] = 0x1230
70 svstate
= SVP64State()
71 # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
72 svstate
.vl
[0:7] = 1 # VL
73 svstate
.maxvl
[0:7] = 1 # MAXVL
74 print("SVSTATE", bin(svstate
.spr
.asint()))
76 self
.add_case(Program(lst
, bigendian
), initial_regs
,
77 initial_svstate
=svstate
)
79 @skip_case("VL hardware loop is not yet implemented")
80 def case_4_sv_check_vl_0(self
):
82 # 1 = 5 + 9 => 0x5555 = 0x4321 + 0x1234
84 'sv.add 13.v, 10.v, 7.v', # skipped, because VL == 0
90 # initial values in GPR regfile
91 initial_regs
= [0] * 32
92 initial_regs
[9] = 0x1234
93 initial_regs
[5] = 0x4321
94 initial_regs
[7] = 0x3012
95 initial_regs
[10] = 0x1230
96 svstate
= SVP64State()
97 # SVSTATE (in this case, VL=0, so vector instructions are skipped)
98 svstate
.vl
[0:7] = 0 # VL
99 svstate
.maxvl
[0:7] = 0 # MAXVL
100 print("SVSTATE", bin(svstate
.spr
.asint()))
102 self
.add_case(Program(lst
, bigendian
), initial_regs
,
103 initial_svstate
=svstate
)