src/soc/fu/alu/test/svp64_cases.py

   1 from soc.fu.test.common import (TestAccumulatorBase, skip_case)
   2 from soc.config.endian import bigendian
   3 from soc.simulator.program import Program
   4 from soc.decoder.isa.caller import SVP64State
   5 from soc.sv.trans.svp64 import SVP64Asm
   6
   7
   8 class SVP64ALUTestCase(TestAccumulatorBase):
   9
  10     @skip_case("VL hardware loop is not yet implemented")
  11     def case_1_sv_add(self):
  12         # adds:
  13         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
  14         #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
  15         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
  16         lst = list(isa)
  17         print("listing", lst)
  18
  19         # initial values in GPR regfile
  20         initial_regs = [0] * 32
  21         initial_regs[9] = 0x1234
  22         initial_regs[10] = 0x1111
  23         initial_regs[5] = 0x4321
  24         initial_regs[6] = 0x2223
  25         # SVSTATE (in this case, VL=2)
  26         svstate = SVP64State()
  27         svstate.vl[0:7] = 2  # VL
  28         svstate.maxvl[0:7] = 2  # MAXVL
  29         print("SVSTATE", bin(svstate.spr.asint()))
  30
  31         self.add_case(Program(lst, bigendian), initial_regs,
  32                       initial_svstate=svstate)
  33
  34     def case_2_sv_add_scalar(self):
  35         # adds:
  36         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
  37         isa = SVP64Asm(['sv.add 1, 5, 9'])
  38         lst = list(isa)
  39         print("listing", lst)
  40
  41         # initial values in GPR regfile
  42         initial_regs = [0] * 32
  43         initial_regs[9] = 0x1234
  44         initial_regs[5] = 0x4321
  45         svstate = SVP64State()
  46         # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
  47         svstate.vl[0:7] = 1  # VL
  48         svstate.maxvl[0:7] = 1  # MAXVL
  49         print("SVSTATE", bin(svstate.spr.asint()))
  50
  51         self.add_case(Program(lst, bigendian), initial_regs,
  52                       initial_svstate=svstate)
  53
  54     # This case helps checking the encoding of the Extra field
  55     # It was built so the v3.0b registers are: 3, 2, 1
  56     # and the Extra field is: 101.110.111
  57     # The expected SVP64 register numbers are: 13, 10, 7
  58     # Any mistake in decoding will probably give a different answer
  59     def case_3_sv_check_extra(self):
  60         # adds:
  61         #       13 = 10 + 7   => 0x4242 = 0x1230 + 0x3012
  62         isa = SVP64Asm(['sv.add 13.v, 10.v, 7.v'])
  63         lst = list(isa)
  64         print("listing", lst)
  65
  66         # initial values in GPR regfile
  67         initial_regs = [0] * 32
  68         initial_regs[7] = 0x3012
  69         initial_regs[10] = 0x1230
  70         svstate = SVP64State()
  71         # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
  72         svstate.vl[0:7] = 1  # VL
  73         svstate.maxvl[0:7] = 1  # MAXVL
  74         print("SVSTATE", bin(svstate.spr.asint()))
  75
  76         self.add_case(Program(lst, bigendian), initial_regs,
  77                       initial_svstate=svstate)