src/soc/fu/alu/test/svp64_cases.py

   1 from soc.fu.test.common import (TestAccumulatorBase, skip_case)
   2 from soc.config.endian import bigendian
   3 from soc.simulator.program import Program
   4 from soc.decoder.isa.caller import SVP64State
   5 from soc.sv.trans.svp64 import SVP64Asm
   6
   7
   8 class SVP64ALUTestCase(TestAccumulatorBase):
   9
  10     def case_1_sv_add(self):
  11         # adds:
  12         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
  13         #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
  14         isa = SVP64Asm(['sv.add 1.v, 5.v, 9.v'])
  15         lst = list(isa)
  16         print("listing", lst)
  17
  18         # initial values in GPR regfile
  19         initial_regs = [0] * 32
  20         initial_regs[9] = 0x1234
  21         initial_regs[10] = 0x1111
  22         initial_regs[5] = 0x4321
  23         initial_regs[6] = 0x2223
  24         # SVSTATE (in this case, VL=2)
  25         svstate = SVP64State()
  26         svstate.vl[0:7] = 2  # VL
  27         svstate.maxvl[0:7] = 2  # MAXVL
  28         print("SVSTATE", bin(svstate.spr.asint()))
  29
  30         self.add_case(Program(lst, bigendian), initial_regs,
  31                       initial_svstate=svstate)
  32
  33     def case_2_sv_add_scalar(self):
  34         # adds:
  35         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
  36         isa = SVP64Asm(['sv.add 1, 5, 9'])
  37         lst = list(isa)
  38         print("listing", lst)
  39
  40         # initial values in GPR regfile
  41         initial_regs = [0] * 32
  42         initial_regs[9] = 0x1234
  43         initial_regs[5] = 0x4321
  44         svstate = SVP64State()
  45         # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
  46         svstate.vl[0:7] = 1  # VL
  47         svstate.maxvl[0:7] = 1  # MAXVL
  48         print("SVSTATE", bin(svstate.spr.asint()))
  49
  50         self.add_case(Program(lst, bigendian), initial_regs,
  51                       initial_svstate=svstate)
  52
  53     # This case helps checking the encoding of the Extra field
  54     # It was built so the v3.0b registers are: 3, 2, 1
  55     # and the Extra field is: 101.110.111
  56     # The expected SVP64 register numbers are: 13, 10, 7
  57     # Any mistake in decoding will probably give a different answer
  58     def case_3_sv_check_extra(self):
  59         # adds:
  60         #       13 = 10 + 7   => 0x4242 = 0x1230 + 0x3012
  61         isa = SVP64Asm(['sv.add 13.v, 10.v, 7.v'])
  62         lst = list(isa)
  63         print("listing", lst)
  64
  65         # initial values in GPR regfile
  66         initial_regs = [0] * 32
  67         initial_regs[7] = 0x3012
  68         initial_regs[10] = 0x1230
  69         svstate = SVP64State()
  70         # SVSTATE (in this case, VL=1, so everything works as in v3.0B)
  71         svstate.vl[0:7] = 1  # VL
  72         svstate.maxvl[0:7] = 1  # MAXVL
  73         print("SVSTATE", bin(svstate.spr.asint()))
  74
  75         self.add_case(Program(lst, bigendian), initial_regs,
  76                       initial_svstate=svstate)
  77
  78     def case_4_sv_add_(self):
  79         # adds when Rc=1:                               TODO CRs higher up
  80         #       1 = 5 + 9   => 0 = -1+1                 CR0=0b100
  81         #       2 = 6 + 10  => 0x3334 = 0x2223+0x1111   CR1=0b010
  82
  83         isa = SVP64Asm(['sv.add. 1.v, 5.v, 9.v'])
  84         lst = list(isa)
  85         print("listing", lst)
  86
  87         # initial values in GPR regfile
  88         initial_regs = [0] * 32
  89         initial_regs[9] = 0xffffffffffffffff
  90         initial_regs[10] = 0x1111
  91         initial_regs[5] = 0x1
  92         initial_regs[6] = 0x2223
  93
  94         # SVSTATE (in this case, VL=2)
  95         svstate = SVP64State()
  96         svstate.vl[0:7] = 2  # VL
  97         svstate.maxvl[0:7] = 2  # MAXVL
  98         print("SVSTATE", bin(svstate.spr.asint()))
  99
 100         self.add_case(Program(lst, bigendian), initial_regs,
 101                       initial_svstate=svstate)
 102
 103     def case_5_sv_check_vl_0(self):
 104         # adds:
 105         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
 106         isa = SVP64Asm([
 107             'sv.add 13.v, 10.v, 7.v',  # skipped, because VL == 0
 108             'add 1, 5, 9'
 109         ])
 110         lst = list(isa)
 111         print("listing", lst)
 112
 113         # initial values in GPR regfile
 114         initial_regs = [0] * 32
 115         initial_regs[9] = 0x1234
 116         initial_regs[5] = 0x4321
 117         initial_regs[7] = 0x3012
 118         initial_regs[10] = 0x1230
 119         svstate = SVP64State()
 120         # SVSTATE (in this case, VL=0, so vector instructions are skipped)
 121         svstate.vl[0:7] = 0  # VL
 122         svstate.maxvl[0:7] = 0  # MAXVL
 123         print("SVSTATE", bin(svstate.spr.asint()))
 124
 125         self.add_case(Program(lst, bigendian), initial_regs,
 126                       initial_svstate=svstate)
 127
 128     # checks that SRCSTEP was reset properly after an SV instruction
 129     def case_6_sv_add_multiple(self):
 130         # adds:
 131         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
 132         #       2 = 6 + 10  => 0x3334 = 0x2223 + 0x1111
 133         #       3 = 7 + 11  => 0x4242 = 0x3012 + 0x1230
 134         #      13 = 10 + 7  => 0x2341 = 0x1111 + 0x1230
 135         #      14 = 11 + 8  => 0x3012 = 0x3012 + 0x0000
 136         #      15 = 12 + 9  => 0x1234 = 0x0000 + 0x1234
 137         isa = SVP64Asm([
 138             'sv.add 1.v, 5.v, 9.v',
 139             'sv.add 13.v, 10.v, 7.v'
 140         ])
 141         lst = list(isa)
 142         print("listing", lst)
 143
 144         # initial values in GPR regfile
 145         initial_regs = [0] * 32
 146         initial_regs[9] = 0x1234
 147         initial_regs[10] = 0x1111
 148         initial_regs[11] = 0x3012
 149         initial_regs[5] = 0x4321
 150         initial_regs[6] = 0x2223
 151         initial_regs[7] = 0x1230
 152         # SVSTATE (in this case, VL=3)
 153         svstate = SVP64State()
 154         svstate.vl[0:7] = 3  # VL
 155         svstate.maxvl[0:7] = 3  # MAXVL
 156         print("SVSTATE", bin(svstate.spr.asint()))
 157
 158         self.add_case(Program(lst, bigendian), initial_regs,
 159                       initial_svstate=svstate)
 160
 161     def case_7_sv_add_2(self):
 162         # adds:
 163         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
 164         #       r1 is scalar so ENDS EARLY
 165         isa = SVP64Asm(['sv.add 1, 5.v, 9.v'])
 166         lst = list(isa)
 167         print("listing", lst)
 168
 169         # initial values in GPR regfile
 170         initial_regs = [0] * 32
 171         initial_regs[9] = 0x1234
 172         initial_regs[10] = 0x1111
 173         initial_regs[5] = 0x4321
 174         initial_regs[6] = 0x2223
 175         # SVSTATE (in this case, VL=2)
 176         svstate = SVP64State()
 177         svstate.vl[0:7] = 2  # VL
 178         svstate.maxvl[0:7] = 2  # MAXVL
 179         print("SVSTATE", bin(svstate.spr.asint()))
 180         self.add_case(Program(lst, bigendian), initial_regs,
 181                       initial_svstate=svstate)
 182
 183     def case_8_sv_add_3(self):
 184         # adds:
 185         #       1 = 5 + 9   => 0x5555 = 0x4321+0x1234
 186         #       2 = 5 + 10  => 0x5432 = 0x4321+0x1111
 187         isa = SVP64Asm(['sv.add 1.v, 5, 9.v'])
 188         lst = list(isa)
 189         print("listing", lst)
 190
 191         # initial values in GPR regfile
 192         initial_regs = [0] * 32
 193         initial_regs[9] = 0x1234
 194         initial_regs[10] = 0x1111
 195         initial_regs[5] = 0x4321
 196         initial_regs[6] = 0x2223
 197         # SVSTATE (in this case, VL=2)
 198         svstate = SVP64State()
 199         svstate.vl[0:7] = 2  # VL
 200         svstate.maxvl[0:7] = 2  # MAXVL
 201         print("SVSTATE", bin(svstate.spr.asint()))
 202         self.add_case(Program(lst, bigendian), initial_regs,
 203                       initial_svstate=svstate)
 204
 205     def case_9_sv_extsw_intpred(self):
 206         # extsb, integer twin-pred mask: source is ~r3 (0b01), dest r3 (0b10)
 207         # works as follows, where any zeros indicate "skip element"
 208         #       - sources are 9 and 10
 209         #       - dests are 5 and 6
 210         #       - source mask says "pick first element from source (5)
 211         #       - dest mask says "pick *second* element from dest (10)
 212         #
 213         # therefore the operation that's carried out is:
 214         #       GPR(10) = extsb(GPR(5))
 215         #
 216         # this is a type of back-to-back VREDUCE and VEXPAND but it applies
 217         # to *operations*, not just MVs like in traditional Vector ISAs
 218         # ascii graphic:
 219         #
 220         #   reg num        0 1 2 3 4 5 6 7 8 9 10
 221         #   src ~r3=0b01                     Y N
 222         #                                    |
 223         #                              +-----+
 224         #                              |
 225         #   dest r3=0b10             N Y
 226
 227         # expected results:
 228         # r5 = 0x0                   dest r3 is 0b10: skip
 229         # r6 = 0xffff_ffff_ffff_ff91 2nd bit of r3 is 1
 230         isa = SVP64Asm(['sv.extsb/sm=~r3/dm=r3 5.v, 9.v'])
 231         lst = list(isa)
 232         print("listing", lst)
 233
 234         # initial values in GPR regfile
 235         initial_regs = [0] * 32
 236         initial_regs[3] = 0b10   # predicate mask
 237         initial_regs[9] = 0x91   # source ~r3 is 0b01 so this will be used
 238         initial_regs[10] = 0x90  # this gets skipped
 239         # SVSTATE (in this case, VL=2)
 240         svstate = SVP64State()
 241         svstate.vl[0:7] = 2  # VL
 242         svstate.maxvl[0:7] = 2  # MAXVL
 243         print("SVSTATE", bin(svstate.spr.asint()))
 244
 245         self.add_case(Program(lst, bigendian), initial_regs,
 246                       initial_svstate=svstate)
 247
 248     def case_10_intpred_vcompress(self):
 249         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 250         #   src r3=0b101                     Y  N  Y
 251         #                                    |     |
 252         #                            +-------+     |
 253         #                            | +-----------+
 254         #                            | |
 255         #   dest always              Y Y Y
 256
 257         # expected results:
 258         # r5 = 0xffff_ffff_ffff_ff90 (from r9)
 259         # r6 = 0xffff_ffff_ffff_ff92 (from r11)
 260         # r7 = 0x0 (VL loop runs out before we can use it)
 261         isa = SVP64Asm(['sv.extsb/sm=r3 5.v, 9.v'])
 262         lst = list(isa)
 263         print("listing", lst)
 264
 265         # initial values in GPR regfile
 266         initial_regs = [0] * 32
 267         initial_regs[3] = 0b101  # predicate mask
 268         initial_regs[9] = 0x90   # source r3 is 0b101 so this will be used
 269         initial_regs[10] = 0x91  # this gets skipped
 270         initial_regs[11] = 0x92  # source r3 is 0b101 so this will be used
 271         # SVSTATE (in this case, VL=3)
 272         svstate = SVP64State()
 273         svstate.vl[0:7] = 3  # VL
 274         svstate.maxvl[0:7] = 3  # MAXVL
 275         print("SVSTATE", bin(svstate.spr.asint()))
 276
 277         self.add_case(Program(lst, bigendian), initial_regs,
 278                       initial_svstate=svstate)
 279
 280     def case_11_intpred_vexpand(self):
 281         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 282         #   src always                       Y  Y  Y
 283         #                                    |  |
 284         #                            +-------+  |
 285         #                            |   +------+
 286         #                            |   |
 287         #   dest r3=0b101            Y N Y
 288
 289         # expected results:
 290         # r5 = 0xffff_ffff_ffff_ff90 1st bit of r3 is 1
 291         # r6 = 0x0                   skip
 292         # r7 = 0xffff_ffff_ffff_ff91 3nd bit of r3 is 1
 293         isa = SVP64Asm(['sv.extsb/dm=r3 5.v, 9.v'])
 294         lst = list(isa)
 295         print("listing", lst)
 296
 297         # initial values in GPR regfile
 298         initial_regs = [0] * 32
 299         initial_regs[3] = 0b101  # predicate mask
 300         initial_regs[9] = 0x90   # source is "always", so this will be used
 301         initial_regs[10] = 0x91  # likewise
 302         initial_regs[11] = 0x92  # the VL loop runs out before we can use it
 303         # SVSTATE (in this case, VL=3)
 304         svstate = SVP64State()
 305         svstate.vl[0:7] = 3  # VL
 306         svstate.maxvl[0:7] = 3  # MAXVL
 307         print("SVSTATE", bin(svstate.spr.asint()))
 308
 309         self.add_case(Program(lst, bigendian), initial_regs,
 310                       initial_svstate=svstate)
 311
 312     def case_12_sv_twinpred(self):
 313         #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
 314         #   src r3=0b101                     Y  N  Y
 315         #                                    |
 316         #                              +-----+
 317         #                              |
 318         #   dest ~r3=0b010           N Y N
 319
 320         # expected results:
 321         # r5 = 0x0                   dest ~r3 is 0b010: skip
 322         # r6 = 0xffff_ffff_ffff_ff90 2nd bit of ~r3 is 1
 323         # r7 = 0x0                   dest ~r3 is 0b010: skip
 324         isa = SVP64Asm(['sv.extsb/sm=r3/dm=~r3 5.v, 9.v'])
 325         lst = list(isa)
 326         print("listing", lst)
 327
 328         # initial values in GPR regfile
 329         initial_regs = [0] * 32
 330         initial_regs[3] = 0b101  # predicate mask
 331         initial_regs[9] = 0x90   # source r3 is 0b101 so this will be used
 332         initial_regs[10] = 0x91  # this gets skipped
 333         initial_regs[11] = 0x92  # VL loop runs out before we can use it
 334         # SVSTATE (in this case, VL=3)
 335         svstate = SVP64State()
 336         svstate.vl[0:7] = 3  # VL
 337         svstate.maxvl[0:7] = 3  # MAXVL
 338         print("SVSTATE", bin(svstate.spr.asint()))
 339
 340         self.add_case(Program(lst, bigendian), initial_regs,
 341                       initial_svstate=svstate)
 342
 343     # checks integer predication.
 344     def case_13_sv_predicated_add(self):
 345         # adds:
 346         #       1 = 5 + 9   => 0x5555 = 0x4321 + 0x1234
 347         #       2 = 0 (skipped)
 348         #       3 = 7 + 11  => 0x4242 = 0x3012 + 0x1230
 349         #
 350         #      13 = 0 (skipped)
 351         #      14 = 11 + 8  => 0xB063 = 0x3012 + 0x8051
 352         #      15 = 0 (skipped)
 353         isa = SVP64Asm([
 354             'sv.add/m=r30 1.v, 5.v, 9.v',
 355             'sv.add/m=~r30 13.v, 10.v, 7.v'
 356         ])
 357         lst = list(isa)
 358         print("listing", lst)
 359
 360         # initial values in GPR regfile
 361         initial_regs = [0] * 32
 362         initial_regs[30] = 0b101  # predicate mask
 363         initial_regs[9] = 0x1234
 364         initial_regs[10] = 0x1111
 365         initial_regs[11] = 0x3012
 366         initial_regs[5] = 0x4321
 367         initial_regs[6] = 0x2223
 368         initial_regs[7] = 0x1230
 369         initial_regs[8] = 0x8051
 370         # SVSTATE (in this case, VL=3)
 371         svstate = SVP64State()
 372         svstate.vl[0:7] = 3  # VL
 373         svstate.maxvl[0:7] = 3  # MAXVL
 374         print("SVSTATE", bin(svstate.spr.asint()))
 375
 376         self.add_case(Program(lst, bigendian), initial_regs,
 377                       initial_svstate=svstate)
 378
 379     # checks an instruction with no effect (all mask bits are zeros)
 380     def case_14_intpred_all_zeros_all_ones(self):
 381         # adds:
 382         #       1 = 0 (skipped)
 383         #       2 = 0 (skipped)
 384         #       3 = 0 (skipped)
 385         #
 386         #      13 = 10 + 7  => 0x2341 = 0x1111 + 0x1230
 387         #      14 = 11 + 8  => 0xB063 = 0x3012 + 0x8051
 388         #      15 = 12 + 9  => 0x7736 = 0x6502 + 0x1234
 389         isa = SVP64Asm([
 390             'sv.add/m=r30 1.v, 5.v, 9.v',
 391             'sv.add/m=~r30 13.v, 10.v, 7.v'
 392         ])
 393         lst = list(isa)
 394         print("listing", lst)
 395
 396         # initial values in GPR regfile
 397         initial_regs = [0] * 32
 398         initial_regs[30] = 0b101  # predicate mask
 399         initial_regs[9] = 0x1234
 400         initial_regs[10] = 0x1111
 401         initial_regs[11] = 0x3012
 402         initial_regs[12] = 0x6502
 403         initial_regs[5] = 0x4321
 404         initial_regs[6] = 0x2223
 405         initial_regs[7] = 0x1230
 406         initial_regs[8] = 0x8051
 407         # SVSTATE (in this case, VL=3)
 408         svstate = SVP64State()
 409         svstate.vl[0:7] = 3  # VL
 410         svstate.maxvl[0:7] = 3  # MAXVL
 411         print("SVSTATE", bin(svstate.spr.asint()))
 412
 413         self.add_case(Program(lst, bigendian), initial_regs,
 414                       initial_svstate=svstate)