2 from soc
.fu
.test
.common
import (TestCase
, TestAccumulatorBase
)
3 from soc
.config
.endian
import bigendian
4 from soc
.simulator
.program
import Program
5 from soc
.decoder
.isa
.caller
import special_sprs
6 from soc
.sv
.trans
.svp64
import SVP64Asm
9 class SVP64ALUTestCase(TestAccumulatorBase
):
11 def case_1_sv_add(self
):
13 # 1 = 5 + 9 => 0x5555 = 0x4321+0x1234
14 # 2 = 6 + 10 => 0x3334 = 0x2223+0x1111
15 isa
= SVP64Asm(['sv.add 1.v, 5.v, 9.v'
18 print ("listing", lst
)
19 initial_regs
= [0] * 32
20 initial_regs
[9] = 0x1234
21 initial_regs
[10] = 0x1111
22 initial_regs
[5] = 0x4321
23 initial_regs
[6] = 0x2223
24 svstate
= SVP64State()
25 svstate
.vl
[0:7] = 2 # VL
26 svstate
.maxvl
[0:7] = 2 # MAXVL
27 print ("SVSTATE", bin(svstate
.spr
.asint()))
29 self
.add_case(Program(lst
, bigendian
), initial_regs
,
30 initial_svstate
=svstate
)