move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / base_input_record.py
1 from nmigen.hdl.rec import Record, Layout
2 from nmigen import Signal
3
4 # needed for SVP64 information at the pipeline
5 from openpower.decoder.power_svp64_rm import sv_input_record_layout
6
7
8 class CompOpSubsetBase(Record):
9 """CompOpSubsetBase
10
11 base class of subset Operation information
12 """
13 def __init__(self, layout, name):
14 if name is None:
15 name = self.__class__.__name__
16 print ("Subset name", name)
17 assert name.startswith("Comp")
18 assert name.endswith("OpSubset")
19 name = name[4:-8].lower() + "_op"
20
21 layout = list(layout) + sv_input_record_layout
22 Record.__init__(self, Layout(layout), name=name)
23
24 # grrr. Record does not have kwargs
25 for fname, sig in self.fields.items():
26 sig.reset_less = True
27
28 def eq_from(self, other):
29 """ use this to copy in from another CompRecord
30 """
31 res = []
32 print ("eq_from self", self, self.fields)
33 print (" other", other, other.fields)
34 for fname, sig in self.fields.items():
35 eqfrom = other.fields[fname]
36 res.append(sig.eq(eqfrom))
37 return res
38
39 def eq_from_execute1(self, other):
40 """ use this to copy in from Decode2Execute1Type
41 """
42 return self.eq_from(other)
43
44 def ports(self):
45 res = []
46 for fname, sig in self.fields.items():
47 if isinstance(sig, Signal):
48 res.append(sig)
49 return res