src/soc/fu/branch/br_input_record.py

   1 from nmigen.hdl.rec import Record, Layout
   2
   3 from soc.decoder.power_enums import InternalOp, Function, CryIn
   4
   5
   6 class CompBROpSubset(Record):
   7     """CompBROpSubset
   8
   9     TODO: remove anything not needed by the Branch pipeline (determine this
  10     after all branch operations have been written.  see
  11     https://bugs.libre-soc.org/show_bug.cgi?id=313#c3)
  12
  13     a copy of the relevant subset information from Decode2Execute1Type
  14     needed for Branch operations.  use with eq_from_execute1 (below) to
  15     grab subsets.
  16     """
  17     def __init__(self, name=None):
  18         layout = (('insn_type', InternalOp),
  19                   ('fn_unit', Function),
  20                   ('imm_data', Layout((("imm", 64), ("imm_ok", 1)))),
  21                    #'cr = Signal(32) # NO: this is from the CR SPR
  22                     #'xerc = XerBits() # NO: this is from the XER SPR
  23                   ('lk', 1),
  24                   ('rc', Layout((("rc", 1), ("rc_ok", 1)))),
  25                   ('oe', Layout((("oe", 1), ("oe_ok", 1)))),
  26                   ('invert_a', 1),
  27                   ('invert_out', 1),
  28                   ('input_carry', CryIn),
  29                   ('output_carry', 1),
  30                   ('input_cr', 1),
  31                   ('output_cr', 1),
  32                   ('is_32bit', 1),
  33                   ('is_signed', 1),
  34                   ('insn', 32),
  35                   ('byte_reverse', 1),
  36                   ('sign_extend', 1))
  37
  38         Record.__init__(self, Layout(layout), name=name)
  39
  40         # grrr.  Record does not have kwargs
  41         self.insn_type.reset_less = True
  42         self.fn_unit.reset_less = True
  43         #self.cr = Signal(32, reset_less = True
  44         #self.xerc = XerBits(
  45         self.lk.reset_less = True
  46         self.invert_a.reset_less = True
  47         self.invert_out.reset_less = True
  48         self.input_carry.reset_less = True
  49         self.output_carry.reset_less = True
  50         self.input_cr.reset_less = True
  51         self.output_cr.reset_less = True
  52         self.is_32bit.reset_less = True
  53         self.is_signed.reset_less = True
  54         self.byte_reverse.reset_less = True
  55         self.sign_extend.reset_less = True
  56
  57     def eq_from_execute1(self, other):
  58         """ use this to copy in from Decode2Execute1Type
  59         """
  60         res = []
  61         for fname, sig in self.fields.items():
  62             eqfrom = other.fields[fname]
  63             res.append(sig.eq(eqfrom))
  64         return res
  65
  66     def ports(self):
  67         return [self.insn_type,
  68                 #self.cr,
  69                 #self.xerc,
  70                 self.lk,
  71                 self.invert_a,
  72                 self.invert_out,
  73                 self.input_carry,
  74                 self.output_carry,
  75                 self.input_cr,
  76                 self.output_cr,
  77                 self.is_32bit,
  78                 self.is_signed,
  79                 self.byte_reverse,
  80                 self.sign_extend,
  81         ]