src/soc/fu/branch/formal/proof_main_stage.py

   1 # Proof of correctness for partitioned equal signal combiner
   2 # Copyright (C) 2020 Michael Nolan <mtnolan2640@gmail.com>
   3
   4 from nmigen import (Module, Signal, Elaboratable, Mux, Cat, Repl,
   5                     signed)
   6 from nmigen.asserts import Assert, AnyConst, Assume, Cover
   7 from nmigen.test.utils import FHDLTestCase
   8 from nmigen.cli import rtlil
   9
  10 from soc.logical.main_stage import LogicalMainStage
  11 from soc.alu.pipe_data import ALUPipeSpec
  12 from soc.alu.alu_input_record import CompALUOpSubset
  13 from soc.decoder.power_enums import InternalOp
  14 import unittest
  15
  16
  17 # This defines a module to drive the device under test and assert
  18 # properties about its outputs
  19 class Driver(Elaboratable):
  20     def __init__(self):
  21         # inputs and outputs
  22         pass
  23
  24     def elaborate(self, platform):
  25         m = Module()
  26         comb = m.d.comb
  27
  28         rec = CompALUOpSubset()
  29         recwidth = 0
  30         # Setup random inputs for dut.op
  31         for p in rec.ports():
  32             width = p.width
  33             recwidth += width
  34             comb += p.eq(AnyConst(width))
  35
  36         pspec = ALUPipeSpec(id_wid=2, op_wid=recwidth)
  37         m.submodules.dut = dut = LogicalMainStage(pspec)
  38
  39         # convenience variables
  40         a = dut.i.a
  41         b = dut.i.b
  42         carry_in = dut.i.carry_in
  43         so_in = dut.i.so
  44         carry_out = dut.o.carry_out
  45         o = dut.o.o
  46
  47         # setup random inputs
  48         comb += [a.eq(AnyConst(64)),
  49                  b.eq(AnyConst(64)),
  50                  carry_in.eq(AnyConst(1)),
  51                  so_in.eq(AnyConst(1))]
  52
  53         comb += dut.i.ctx.op.eq(rec)
  54
  55         # Assert that op gets copied from the input to output
  56         for rec_sig in rec.ports():
  57             name = rec_sig.name
  58             dut_sig = getattr(dut.o.ctx.op, name)
  59             comb += Assert(dut_sig == rec_sig)
  60
  61         # signed and signed/32 versions of input a
  62         a_signed = Signal(signed(64))
  63         a_signed_32 = Signal(signed(32))
  64         comb += a_signed.eq(a)
  65         comb += a_signed_32.eq(a[0:32])
  66
  67         # main assertion of arithmetic operations
  68         with m.Switch(rec.insn_type):
  69             with m.Case(InternalOp.OP_AND):
  70                 comb += Assert(dut.o.o == a & b)
  71             with m.Case(InternalOp.OP_OR):
  72                 comb += Assert(dut.o.o == a | b)
  73             with m.Case(InternalOp.OP_XOR):
  74                 comb += Assert(dut.o.o == a ^ b)
  75
  76         return m
  77
  78
  79 class LogicalTestCase(FHDLTestCase):
  80     def test_formal(self):
  81         module = Driver()
  82         self.assertFormal(module, mode="bmc", depth=2)
  83         self.assertFormal(module, mode="cover", depth=2)
  84     def test_ilang(self):
  85         dut = Driver()
  86         vl = rtlil.convert(dut, ports=[])
  87         with open("main_stage.il", "w") as f:
  88             f.write(vl)
  89
  90
  91 if __name__ == '__main__':
  92     unittest.main()