src/soc/fu/branch/pipe_data.py

   1 """
   2     Optional Register allocation listed below.  mandatory input
   3     (CompBROpSubset, CIA) not included.
   4
   5     * CR is Condition Register (not an SPR)
   6     * SPR1, SPR2 and SPR3 are all from the SPR regfile.  3 ports are needed
   7
   8     insn       CR  SPR1  SPR2    SPR3
   9     ----       --  ----  ----    ----
  10     op_b       xx  xx     xx     xx
  11     op_ba      xx  xx     xx     xx
  12     op_bl      xx  xx     xx     xx
  13     op_bla     xx  xx     xx     xx
  14     op_bc      CR, xx,    CTR    xx
  15     op_bca     CR, xx,    CTR    xx
  16     op_bcl     CR, xx,    CTR    xx
  17     op_bcla    CR, xx,    CTR    xx
  18     op_bclr    CR, LR,    CTR    xx
  19     op_bclrl   CR, LR,    CTR    xx
  20     op_bcctr   CR, xx,    CTR    xx
  21     op_bcctrl  CR, xx,    CTR    xx
  22     op_bctar   CR, TAR,   CTR,   xx
  23     op_bctarl  CR, TAR,   CTR,   xx
  24
  25     op_sc      xx  xx     xx     MSR
  26     op_scv     xx  LR,    SRR1,  MSR
  27     op_rfscv   xx  LR,    CTR,   MSR
  28     op_rfid    xx  SRR0,  SRR1,  MSR
  29     op_hrfid   xx  HSRR0, HSRR1, MSR
  30 """
  31
  32 from nmigen import Signal, Const
  33 from ieee754.fpcommon.getop import FPPipeContext
  34 from soc.decoder.power_decoder2 import Data
  35 from soc.alu.pipe_data import IntegerData
  36
  37
  38 class BranchInputData(IntegerData):
  39     def __init__(self, pspec):
  40         super().__init__(pspec)
  41         # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
  42         # this involves the *decode* unit selecting the register, based
  43         # on detecting the operand being bcctr, bclr or bctar
  44
  45         self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
  46         self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
  47         self.spr3 = Signal(64, reset_less=True) # see table above, SPR3
  48         self.cr = Signal(32, reset_less=True)   # Condition Register(s) CR0-7
  49         self.cia = Signal(64, reset_less=True)  # Current Instruction Address
  50
  51         # convenience variables.  not all of these are used at once
  52         self.ctr = self.srr0 = self.hsrr0 = self.spr2
  53         self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr1
  54         self.msr = self.spr3
  55
  56     def __iter__(self):
  57         yield from super().__iter__()
  58         yield self.spr1
  59         yield self.spr2
  60         yield self.spr3
  61         yield self.cr
  62         yield self.cia
  63
  64     def eq(self, i):
  65         lst = super().eq(i)
  66         return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
  67                       self.spr3.eq(i.spr3),
  68                       self.cr.eq(i.cr), self.cia.eq(i.cia)]
  69
  70
  71 class BranchOutputData(IntegerData):
  72     def __init__(self, pspec):
  73         super().__init__(pspec)
  74         self.lr = Data(64, name="lr")
  75         self.spr = Data(64, name="spr")
  76         self.nia = Data(64, name="nia")
  77
  78         # convenience variables.
  79         self.ctr = self.spr
  80
  81     def __iter__(self):
  82         yield from super().__iter__()
  83         yield from self.lr
  84         yield from self.spr
  85         yield from self.nia
  86
  87     def eq(self, i):
  88         lst = super().eq(i)
  89         return lst + [self.lr.eq(i.lr), self.spr.eq(i.spr),
  90                       self.nia.eq(i.nia)]