src/soc/fu/branch/pipe_data.py

   1 """
   2     Optional Register allocation listed below.  mandatory input
   3     (CompBROpSubset, CIA) not included.
   4
   5     * CR is Condition Register (not an SPR)
   6     * SPR1 and SPR2 are all from the SPR regfile.  2 ports are needed
   7
   8     insn       CR  SPR1  SPR2
   9     ----       --  ----  ----
  10     op_b       xx  xx     xx
  11     op_ba      xx  xx     xx
  12     op_bl      xx  xx     xx
  13     op_bla     xx  xx     xx
  14     op_bc      CR, xx,    CTR
  15     op_bca     CR, xx,    CTR
  16     op_bcl     CR, xx,    CTR
  17     op_bcla    CR, xx,    CTR
  18     op_bclr    CR, LR,    CTR
  19     op_bclrl   CR, LR,    CTR
  20     op_bcctr   CR, xx,    CTR
  21     op_bcctrl  CR, xx,    CTR
  22     op_bctar   CR, TAR,   CTR
  23     op_bctarl  CR, TAR,   CTR
  24 """
  25
  26 from nmigen import Signal, Const
  27 from ieee754.fpcommon.getop import FPPipeContext
  28 from soc.decoder.power_decoder2 import Data
  29 from soc.fu.alu.pipe_data import IntegerData
  30 from nmutil.dynamicpipe import SimpleHandshakeRedir
  31 from soc.fu.alu.alu_input_record import CompALUOpSubset # TODO: replace
  32
  33
  34 class BranchInputData(IntegerData):
  35     regspec = [('SPR', 'spr1', '0:63'),
  36                ('SPR', 'spr2', '0:63'),
  37                ('CR', 'cr', '32'),
  38                ('PC', 'cia', '0:63')]
  39     def __init__(self, pspec):
  40         super().__init__(pspec)
  41         # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
  42         # this involves the *decode* unit selecting the register, based
  43         # on detecting the operand being bcctr, bclr or bctar
  44
  45         self.spr1 = Signal(64, reset_less=True) # see table above, SPR1
  46         self.spr2 = Signal(64, reset_less=True) # see table above, SPR2
  47         self.cr = Signal(32, reset_less=True)   # Condition Register(s) CR0-7
  48         self.cia = Signal(64, reset_less=True)  # Current Instruction Address
  49
  50         # convenience variables.  not all of these are used at once
  51         self.ctr = self.srr0 = self.hsrr0 = self.spr2
  52         self.lr = self.tar = self.srr1 = self.hsrr1 = self.spr1
  53
  54     def __iter__(self):
  55         yield from super().__iter__()
  56         yield self.spr1
  57         yield self.spr2
  58         yield self.cr
  59         yield self.cia
  60
  61     def eq(self, i):
  62         lst = super().eq(i)
  63         return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
  64                       self.cr.eq(i.cr), self.cia.eq(i.cia)]
  65
  66
  67 class BranchOutputData(IntegerData):
  68     regspec = [('SPR', 'spr1', '0:63'),
  69                ('SPR', 'spr2', '0:63'),
  70                ('PC', 'nia', '0:63')]
  71     def __init__(self, pspec):
  72         super().__init__(pspec)
  73         self.spr1 = Data(64, name="spr1")
  74         self.spr2 = Data(64, name="spr2")
  75         self.nia = Data(64, name="nia")
  76
  77         # convenience variables.
  78         self.lr = self.tar = self.spr1
  79         self.ctr = self.spr2
  80
  81     def __iter__(self):
  82         yield from super().__iter__()
  83         yield from self.spr1
  84         yield from self.spr2
  85         yield from self.nia
  86
  87     def eq(self, i):
  88         lst = super().eq(i)
  89         return lst + [self.spr1.eq(i.spr1), self.spr2.eq(i.spr2),
  90                       self.nia.eq(i.nia)]
  91
  92
  93 # TODO: replace CompALUOpSubset with CompBranchOpSubset
  94 class BranchPipeSpec:
  95     regspec = (BranchInputData.regspec, BranchOutputData.regspec)
  96     opsubsetkls = CompALUOpSubset
  97     def __init__(self, id_wid, op_wid):
  98         self.id_wid = id_wid
  99         self.op_wid = op_wid
 100         self.opkls = lambda _: self.opsubsetkls(name="op")
 101         self.stage = None
 102         self.pipekls = SimpleHandshakeRedir