2772236eb61403fef7f64c894d29031d4b12b4e1
2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
23 op_bctarl CR, TAR, CTR
26 from nmigen
import Signal
, Const
27 from ieee754
.fpcommon
.getop
import FPPipeContext
28 from soc
.decoder
.power_decoder2
import Data
29 from soc
.fu
.alu
.pipe_data
import IntegerData
32 class BranchInputData(IntegerData
):
33 def __init__(self
, pspec
):
34 super().__init
__(pspec
)
35 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
36 # this involves the *decode* unit selecting the register, based
37 # on detecting the operand being bcctr, bclr or bctar
39 self
.spr1
= Signal(64, reset_less
=True) # see table above, SPR1
40 self
.spr2
= Signal(64, reset_less
=True) # see table above, SPR2
41 self
.cr
= Signal(32, reset_less
=True) # Condition Register(s) CR0-7
42 self
.cia
= Signal(64, reset_less
=True) # Current Instruction Address
44 # convenience variables. not all of these are used at once
45 self
.ctr
= self
.srr0
= self
.hsrr0
= self
.spr2
46 self
.lr
= self
.tar
= self
.srr1
= self
.hsrr1
= self
.spr1
49 yield from super().__iter
__()
57 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),
58 self
.cr
.eq(i
.cr
), self
.cia
.eq(i
.cia
)]
61 class BranchOutputData(IntegerData
):
62 def __init__(self
, pspec
):
63 super().__init
__(pspec
)
64 self
.spr1
= Data(64, name
="spr1")
65 self
.spr2
= Data(64, name
="spr2")
66 self
.nia
= Data(64, name
="nia")
68 # convenience variables.
69 self
.lr
= self
.tar
= self
.spr1
73 yield from super().__iter
__()
80 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),