74edaa1f75e21a39ad9a680e79e879d97ac8493a
2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
23 op_bctarl CR, TAR, CTR
26 from nmigen
import Signal
, Const
, Cat
27 from ieee754
.fpcommon
.getop
import FPPipeContext
28 from soc
.decoder
.power_decoder2
import Data
29 from soc
.fu
.pipe_data
import IntegerData
, CommonPipeSpec
30 from soc
.fu
.branch
.br_input_record
import CompBROpSubset
# TODO: replace
33 class BranchInputData(IntegerData
):
34 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
35 # this involves the *decode* unit selecting the register, based
36 # on detecting the operand being bcctr, bclr or bctar
37 regspec
= [('FAST', 'spr1', '0:63'), # see table above, SPR1
38 ('FAST', 'spr2', '0:63'), # see table above, SPR2
39 ('CR', 'cr_a', '0:3'), # Condition Register(s) CR0-7
40 ('FAST', 'cia', '0:63')] # Current Instruction Address
41 def __init__(self
, pspec
):
42 super().__init
__(pspec
, False)
44 # convenience variables. not all of these are used at once
46 self
.lr
= self
.tar
= self
.spr2
50 class BranchOutputData(IntegerData
):
51 regspec
= [('FAST', 'spr1', '0:63'),
52 ('FAST', 'spr2', '0:63'),
53 ('FAST', 'nia', '0:63')]
54 def __init__(self
, pspec
):
55 super().__init
__(pspec
, True)
57 # convenience variables.
59 self
.lr
= self
.tar
= self
.spr2
62 class BranchPipeSpec(CommonPipeSpec
):
63 regspec
= (BranchInputData
.regspec
, BranchOutputData
.regspec
)
64 opsubsetkls
= CompBROpSubset