rename IntegerData to FUBaseData
[soc.git] / src / soc / fu / branch / pipe_data.py
1 """
2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
4
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
7
8 insn CR SPR2 SPR1
9 ---- -- ---- ----
10 op_b xx xx xx
11 op_ba xx xx xx
12 op_bl xx xx xx
13 op_bla xx xx xx
14 op_bc CR, xx, CTR
15 op_bca CR, xx, CTR
16 op_bcl CR, xx, CTR
17 op_bcla CR, xx, CTR
18 op_bclr CR, LR, CTR
19 op_bclrl CR, LR, CTR
20 op_bcctr CR, xx, CTR
21 op_bcctrl CR, xx, CTR
22 op_bctar CR, TAR, CTR
23 op_bctarl CR, TAR, CTR
24 """
25
26 from soc.fu.pipe_data import FUBaseData, CommonPipeSpec
27 from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
28
29
30 class BranchInputData(FUBaseData):
31 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
32 # this involves the *decode* unit selecting the register, based
33 # on detecting the operand being bcctr, bclr or bctar
34 regspec = [('FAST', 'fast1', '0:63'), # see table above, SPR1
35 ('FAST', 'fast2', '0:63'), # see table above, SPR2
36 ('CR', 'cr_a', '0:3'), # Condition Register(s) CR0-7
37 ]
38 def __init__(self, pspec):
39 super().__init__(pspec, False)
40
41 # convenience variables. not all of these are used at once
42 self.ctr = self.fast1
43 self.lr = self.tar = self.fast2
44 self.cr = self.cr_a
45
46
47 class BranchOutputData(FUBaseData):
48 regspec = [('FAST', 'fast1', '0:63'),
49 ('FAST', 'fast2', '0:63'),
50 ('STATE', 'nia', '0:63')]
51 def __init__(self, pspec):
52 super().__init__(pspec, True)
53
54 # convenience variables.
55 self.ctr = self.fast1
56 self.lr = self.tar = self.fast2
57
58
59 class BranchPipeSpec(CommonPipeSpec):
60 regspec = (BranchInputData.regspec, BranchOutputData.regspec)
61 opsubsetkls = CompBROpSubset