e75f9e966c70876a089d5093a743b24e3e54b1c2
2 Optional Register allocation listed below. mandatory input
3 (CompBROpSubset, CIA) not included.
5 * CR is Condition Register (not an SPR)
6 * SPR1 and SPR2 are all from the SPR regfile. 2 ports are needed
23 op_bctarl CR, TAR, CTR
26 from nmigen
import Signal
, Const
27 from ieee754
.fpcommon
.getop
import FPPipeContext
28 from soc
.decoder
.power_decoder2
import Data
29 from soc
.fu
.alu
.pipe_data
import IntegerData
30 from nmutil
.dynamicpipe
import SimpleHandshakeRedir
31 from soc
.fu
.alu
.alu_input_record
import CompALUOpSubset
# TODO: replace
33 class BranchInputData(IntegerData
):
34 regspec
= [('SPR', 'spr1', '0:63'),
35 ('SPR', 'spr2', '0:63'),
37 ('PC', 'cia', '0:63')]
38 def __init__(self
, pspec
):
39 super().__init
__(pspec
)
40 # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
41 # this involves the *decode* unit selecting the register, based
42 # on detecting the operand being bcctr, bclr or bctar
44 self
.spr1
= Signal(64, reset_less
=True) # see table above, SPR1
45 self
.spr2
= Signal(64, reset_less
=True) # see table above, SPR2
46 self
.cr
= Signal(32, reset_less
=True) # Condition Register(s) CR0-7
47 self
.cia
= Signal(64, reset_less
=True) # Current Instruction Address
49 # convenience variables. not all of these are used at once
50 self
.ctr
= self
.srr0
= self
.hsrr0
= self
.spr2
51 self
.lr
= self
.tar
= self
.srr1
= self
.hsrr1
= self
.spr1
54 yield from super().__iter
__()
62 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),
63 self
.cr
.eq(i
.cr
), self
.cia
.eq(i
.cia
)]
66 class BranchOutputData(IntegerData
):
67 regspec
= [('SPR', 'spr1', '0:63'),
68 ('SPR', 'spr2', '0:63'),
69 ('PC', 'cia', '0:63')]
70 def __init__(self
, pspec
):
71 super().__init
__(pspec
)
72 self
.spr1
= Data(64, name
="spr1")
73 self
.spr2
= Data(64, name
="spr2")
74 self
.nia
= Data(64, name
="nia")
76 # convenience variables.
77 self
.lr
= self
.tar
= self
.spr1
81 yield from super().__iter
__()
88 return lst
+ [self
.spr1
.eq(i
.spr1
), self
.spr2
.eq(i
.spr2
),
92 # TODO: replace CompALUOpSubset with CompBranchOpSubset
94 regspec
= (BranchInputData
.regspec
, BranchOutputData
.regspec
)
95 def __init__(self
, id_wid
, op_wid
):
98 self
.opkls
= lambda _
: CompALUOpSubset(name
="op")
100 self
.pipekls
= SimpleHandshakeRedir