src/soc/fu/branch/pipe_data.py

   1 """
   2     Optional Register allocation listed below.  mandatory input
   3     (CompBROpSubset, CIA) not included.
   4
   5     * CR is Condition Register (not an SPR)
   6     * SPR1 and SPR2 are all from the SPR regfile.  2 ports are needed
   7
   8     insn       CR  SPR2  SPR1
   9     ----       --  ----  ----
  10     op_b       xx  xx     xx
  11     op_ba      xx  xx     xx
  12     op_bl      xx  xx     xx
  13     op_bla     xx  xx     xx
  14     op_bc      CR, xx,    CTR
  15     op_bca     CR, xx,    CTR
  16     op_bcl     CR, xx,    CTR
  17     op_bcla    CR, xx,    CTR
  18     op_bclr    CR, LR,    CTR
  19     op_bclrl   CR, LR,    CTR
  20     op_bcctr   CR, xx,    CTR
  21     op_bcctrl  CR, xx,    CTR
  22     op_bctar   CR, TAR,   CTR
  23     op_bctarl  CR, TAR,   CTR
  24 """
  25
  26 from nmigen import Signal, Const, Cat
  27 from ieee754.fpcommon.getop import FPPipeContext
  28 from soc.decoder.power_decoder2 import Data
  29 from soc.fu.pipe_data import IntegerData, CommonPipeSpec
  30 from soc.fu.branch.br_input_record import CompBROpSubset # TODO: replace
  31
  32
  33 class BranchInputData(IntegerData):
  34     # Note: for OP_BCREG, SPR1 will either be CTR, LR, or TAR
  35     # this involves the *decode* unit selecting the register, based
  36     # on detecting the operand being bcctr, bclr or bctar
  37     regspec = [('FAST', 'spr1', '0:63'), # see table above, SPR1
  38                ('FAST', 'spr2', '0:63'), # see table above, SPR2
  39                ('CR', 'cr_a', '0:3'),    # Condition Register(s) CR0-7
  40                ('FAST', 'cia', '0:63')]  # Current Instruction Address
  41     def __init__(self, pspec):
  42         super().__init__(pspec, False)
  43
  44         # convenience variables.  not all of these are used at once
  45         self.ctr = self.spr1
  46         self.lr = self.tar = self.spr2
  47         self.cr = self.cr_a
  48
  49
  50 class BranchOutputData(IntegerData):
  51     regspec = [('FAST', 'spr1', '0:63'),
  52                ('FAST', 'spr2', '0:63'),
  53                ('FAST', 'nia', '0:63')]
  54     def __init__(self, pspec):
  55         super().__init__(pspec, True)
  56
  57         # convenience variables.
  58         self.ctr = self.spr1
  59         self.lr = self.tar = self.spr2
  60
  61
  62 class BranchPipeSpec(CommonPipeSpec):
  63     regspec = (BranchInputData.regspec, BranchOutputData.regspec)
  64     opsubsetkls = CompBROpSubset