src/soc/fu/common_input_stage.py

   1 # This stage is intended to adjust the input data before sending it to
   2 # the acutal ALU. Things like handling inverting the input, carry_in
   3 # generation for subtraction, should happen here
   4 from nmigen import (Module, Signal)
   5 from nmutil.pipemodbase import PipeModBase
   6 from soc.decoder.power_enums import InternalOp
   7 from soc.decoder.power_enums import CryIn
   8
   9
  10 class CommonInputStage(PipeModBase):
  11
  12     def elaborate(self, platform):
  13         m = Module()
  14         comb = m.d.comb
  15
  16         ##### operand A #####
  17
  18         # operand a to be as-is or inverted
  19         a = Signal.like(self.i.a)
  20
  21         with m.If(self.i.ctx.op.invert_a):
  22             comb += a.eq(~self.i.a)
  23         with m.Else():
  24             comb += a.eq(self.i.a)
  25
  26         comb += self.o.a.eq(a)
  27
  28         ##### carry-in #####
  29
  30         # either copy incoming carry or set to 1/0 as defined by op
  31         if hasattr(self.i, "xer_ca"): # hack (for now - for LogicalInputData)
  32             with m.Switch(self.i.ctx.op.input_carry):
  33                 with m.Case(CryIn.ZERO):
  34                     comb += self.o.xer_ca.eq(0b00)
  35                 with m.Case(CryIn.ONE):
  36                     comb += self.o.xer_ca.eq(0b11) # XER CA/CA32
  37                 with m.Case(CryIn.CA):
  38                     comb += self.o.xer_ca.eq(self.i.xer_ca)
  39
  40         ##### sticky overflow and context (both pass-through) #####
  41
  42         if hasattr(self.o, "xer_so"): # hack (for now - for LogicalInputData)
  43             comb += self.o.xer_so.eq(self.i.xer_so)
  44         comb += self.o.ctx.eq(self.i.ctx)
  45
  46         return m