src/soc/fu/common_output_stage.py

   1 # This stage is intended to handle the gating of carry out,
   2 # and updating the condition register
   3 from nmigen import (Module, Signal, Cat, Const)
   4 from nmutil.pipemodbase import PipeModBase
   5 from ieee754.part.partsig import PartitionedSignal
   6 from soc.decoder.power_enums import InternalOp
   7
   8
   9 class CommonOutputStage(PipeModBase):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "output")
  12
  13     def elaborate(self, platform):
  14         m = Module()
  15         comb = m.d.comb
  16         op = self.i.ctx.op
  17         if hasattr(self.o, "xer_so"):
  18             xer_so_o = self.o.xer_so.data[0]
  19         else:
  20             xer_so_o = Const(0, 1)
  21
  22         # op requests inversion of the output...
  23         o = Signal.like(self.i.o)
  24         if hasattr(op, "invert_out"): # ... optionally
  25             with m.If(op.invert_out):
  26                 comb += o.eq(~self.i.o.data)
  27             with m.Else():
  28                 comb += o.eq(self.i.o.data)
  29         else:
  30             comb += o.eq(self.i.o.data) # ... no inversion
  31
  32         # target register if 32-bit is only the 32 LSBs
  33         # XXX ah.  right.  this needs to be done only if the *mode* is 32-bit
  34         # see https://bugs.libre-soc.org/show_bug.cgi?id=424
  35         target = Signal(64, reset_less=True)
  36         #with m.If(op.is_32bit):
  37         #    comb += target.eq(o[:32])
  38         #with m.Else():
  39         #    comb += target.eq(o)
  40         comb += target.eq(o)
  41
  42         # carry-out only if actually present in this input spec
  43         # (note: MUL and DIV do not have it, but ALU and Logical do)
  44         if hasattr(self.i, "xer_ca"):
  45             # Handle carry_out
  46             comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
  47             comb += self.o.xer_ca.ok.eq(op.output_carry)
  48
  49         # create condition register cr0 and sticky-overflow
  50         is_nzero = Signal(reset_less=True)
  51         is_positive = Signal(reset_less=True)
  52         is_negative = Signal(reset_less=True)
  53         msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
  54         is_cmp = Signal(reset_less=True)     # true if OP=CMP
  55         is_cmpeqb = Signal(reset_less=True)  # true if OP=CMPEQB
  56         self.so = Signal(1, reset_less=True)
  57         cr0 = Signal(4, reset_less=True)
  58
  59         # TODO: if o[63] is XORed with "operand == OP_CMP"
  60         # that can be used as a test of whether to invert the +ve/-ve test
  61         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
  62
  63         comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
  64         comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
  65         # nope - if *processor* mode is 32-bit
  66         #with m.If(op.is_32bit):
  67         #    comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
  68         #with m.Else():
  69         #    comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
  70         comb += msb_test.eq(target[-1]) # 64-bit MSB
  71         comb += is_nzero.eq(target.bool())
  72         with m.If(is_cmp): # invert pos/neg tests
  73             comb += is_positive.eq(msb_test)
  74             comb += is_negative.eq(is_nzero & ~msb_test)
  75         with m.Else():
  76             comb += is_negative.eq(msb_test)
  77             comb += is_positive.eq(is_nzero & ~msb_test)
  78
  79         with m.If(is_cmpeqb):
  80             comb += cr0.eq(self.i.cr0.data)
  81         with m.Else():
  82             comb += cr0.eq(Cat(xer_so_o, ~is_nzero, is_positive, is_negative))
  83
  84         # copy out [inverted?] output, cr0, and context out
  85         comb += self.o.o.data.eq(o)
  86         comb += self.o.o.ok.eq(self.i.o.ok)
  87         # CR0 to be set
  88         comb += self.o.cr0.data.eq(cr0)
  89         comb += self.o.cr0.ok.eq(op.write_cr0)
  90         # context
  91         comb += self.o.ctx.eq(self.i.ctx)
  92
  93         return m