move pc_i and svstate_i inside if self.run_hdl
[soc.git] / src / soc / fu / common_output_stage.py
1 # This stage is intended to handle the gating of carry out,
2 # and updating the condition register
3 from nmigen import (Module, Signal, Cat, Const)
4 from nmutil.pipemodbase import PipeModBase
5 from ieee754.part.partsig import PartitionedSignal
6 from openpower.decoder.power_enums import MicrOp
7
8
9 class CommonOutputStage(PipeModBase):
10 def __init__(self, pspec):
11 super().__init__(pspec, "output")
12
13 def elaborate(self, platform):
14 m = Module()
15 comb = m.d.comb
16 op = self.i.ctx.op
17 # ok so there are two different ways this goes:
18 # (1) something involving XER ov in which case so gets modified
19 # and that means we need the modified version of so in CR0
20 # (2) something that does *not* have XER ov, in which case so
21 # has been pass-through just to get it into CR0
22 # in case (1) we don't *have* an xer_so output so put xer_so *input*
23 # into CR0.
24 xer_so_i = self.i.xer_so.data[0]
25 if hasattr(self.o, "xer_so"):
26 xer_so_o = self.o.xer_so.data[0]
27 so = Signal(reset_less=True)
28 oe = Signal(reset_less=True)
29 comb += oe.eq(op.oe.oe & op.oe.ok)
30 with m.If(oe):
31 comb += so.eq(xer_so_o)
32 with m.Else():
33 comb += so.eq(xer_so_i)
34 else:
35 so = xer_so_i
36
37 with m.If(~op.sv_pred_dz): # when SVP64 zeroing is set, output is zero
38 # op requests inversion of the output...
39 o = Signal.like(self.i.o)
40 if hasattr(op, "invert_out"): # ... optionally
41 with m.If(op.invert_out):
42 comb += o.eq(~self.i.o.data)
43 with m.Else():
44 comb += o.eq(self.i.o.data)
45 else:
46 comb += o.eq(self.i.o.data) # ... no inversion
47
48 # target register if 32-bit is only the 32 LSBs
49 # XXX ah. right. this needs to be done only if the *mode* is 32-bit
50 # (an MSR bit)
51 # see https://bugs.libre-soc.org/show_bug.cgi?id=424
52 target = Signal(64, reset_less=True)
53 #with m.If(op.is_32bit):
54 # comb += target.eq(o[:32])
55 #with m.Else():
56 # comb += target.eq(o)
57 comb += target.eq(o)
58
59 # carry-out only if actually present in this input spec
60 # (note: MUL and DIV do not have it, but ALU and Logical do)
61 if hasattr(self.i, "xer_ca"):
62 # Handle carry_out
63 comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
64 comb += self.o.xer_ca.ok.eq(op.output_carry)
65
66 # create condition register cr0 and sticky-overflow
67 is_nzero = Signal(reset_less=True)
68 is_positive = Signal(reset_less=True)
69 is_negative = Signal(reset_less=True)
70 msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
71 is_cmp = Signal(reset_less=True) # true if OP=CMP
72 is_cmpeqb = Signal(reset_less=True) # true if OP=CMPEQB
73 cr0 = Signal(4, reset_less=True)
74
75 # TODO: if o[63] is XORed with "operand == OP_CMP"
76 # that can be used as a test of whether to invert the +ve/-ve test
77 # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
78
79 comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
80 comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
81
82 comb += msb_test.eq(target[-1]) # 64-bit MSB, TODO 32-bit MSB
83 comb += is_nzero.eq(target.bool())
84 comb += is_negative.eq(msb_test)
85 comb += is_positive.eq(is_nzero & ~msb_test)
86
87 with m.If(is_cmpeqb | is_cmp):
88 comb += cr0.eq(self.i.cr0.data)
89 with m.Else():
90 comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative))
91
92 # copy out [inverted?] output, cr0, and context out
93 comb += self.o.o.data.eq(o)
94 comb += self.o.o.ok.eq(self.i.o.ok)
95 comb += self.o.cr0.data.eq(cr0) # CR0 to be set
96 comb += self.o.cr0.ok.eq(op.write_cr0)
97 comb += self.o.ctx.eq(self.i.ctx) # context
98
99 return m