src/soc/fu/common_output_stage.py

   1 # This stage is intended to handle the gating of carry out,
   2 # and updating the condition register
   3 from nmigen import (Module, Signal, Cat, Const)
   4 from nmutil.pipemodbase import PipeModBase
   5 from ieee754.part.partsig import PartitionedSignal
   6 from soc.decoder.power_enums import MicrOp
   7
   8
   9 class CommonOutputStage(PipeModBase):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "output")
  12
  13     def elaborate(self, platform):
  14         m = Module()
  15         comb = m.d.comb
  16         op = self.i.ctx.op
  17         # ok so there are two different ways this goes:
  18         # (1) something involving XER ov in which case so gets modified
  19         #     and that means we need the modified version of so in CR0
  20         # (2) something that does *not* have XER ov, in which case so
  21         #     has been pass-through just to get it into CR0
  22         # in case (1) we don't *have* an xer_so output so put xer_so *input*
  23         # into CR0.
  24         xer_so_i = self.i.xer_so.data[0]
  25         if hasattr(self.o, "xer_so"):
  26             xer_so_o = self.o.xer_so.data[0]
  27             so = Signal(reset_less=True)
  28             oe = Signal(reset_less=True)
  29             comb += oe.eq(op.oe.oe & op.oe.oe_ok)
  30             with m.If(oe):
  31                 comb += so.eq(xer_so_o)
  32             with m.Else():
  33                 comb += so.eq(xer_so_i)
  34         else:
  35             so = xer_so_i
  36
  37         # op requests inversion of the output...
  38         o = Signal.like(self.i.o)
  39         if hasattr(op, "invert_out"): # ... optionally
  40             with m.If(op.invert_out):
  41                 comb += o.eq(~self.i.o.data)
  42             with m.Else():
  43                 comb += o.eq(self.i.o.data)
  44         else:
  45             comb += o.eq(self.i.o.data) # ... no inversion
  46
  47         # target register if 32-bit is only the 32 LSBs
  48         # XXX ah.  right.  this needs to be done only if the *mode* is 32-bit
  49         # see https://bugs.libre-soc.org/show_bug.cgi?id=424
  50         target = Signal(64, reset_less=True)
  51         #with m.If(op.is_32bit):
  52         #    comb += target.eq(o[:32])
  53         #with m.Else():
  54         #    comb += target.eq(o)
  55         comb += target.eq(o)
  56
  57         # carry-out only if actually present in this input spec
  58         # (note: MUL and DIV do not have it, but ALU and Logical do)
  59         if hasattr(self.i, "xer_ca"):
  60             # Handle carry_out
  61             comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
  62             comb += self.o.xer_ca.ok.eq(op.output_carry)
  63
  64         # create condition register cr0 and sticky-overflow
  65         is_nzero = Signal(reset_less=True)
  66         is_positive = Signal(reset_less=True)
  67         is_negative = Signal(reset_less=True)
  68         msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
  69         is_cmp = Signal(reset_less=True)     # true if OP=CMP
  70         is_cmpeqb = Signal(reset_less=True)  # true if OP=CMPEQB
  71         cr0 = Signal(4, reset_less=True)
  72
  73         # TODO: if o[63] is XORed with "operand == OP_CMP"
  74         # that can be used as a test of whether to invert the +ve/-ve test
  75         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
  76
  77         comb += is_cmp.eq(op.insn_type == MicrOp.OP_CMP)
  78         comb += is_cmpeqb.eq(op.insn_type == MicrOp.OP_CMPEQB)
  79         # nope - if *processor* mode is 32-bit
  80         #with m.If(op.is_32bit):
  81         #    comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
  82         #with m.Else():
  83         #    comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
  84         comb += msb_test.eq(target[-1]) # 64-bit MSB
  85         comb += is_nzero.eq(target.bool())
  86         with m.If(is_cmp): # invert pos/neg tests
  87             comb += is_positive.eq(msb_test)
  88             comb += is_negative.eq(is_nzero & ~msb_test)
  89         with m.Else():
  90             comb += is_negative.eq(msb_test)
  91             comb += is_positive.eq(is_nzero & ~msb_test)
  92
  93         with m.If(is_cmpeqb):
  94             comb += cr0.eq(self.i.cr0.data)
  95         with m.Else():
  96             comb += cr0.eq(Cat(so, ~is_nzero, is_positive, is_negative))
  97
  98         # copy out [inverted?] output, cr0, and context out
  99         comb += self.o.o.data.eq(o)
 100         comb += self.o.o.ok.eq(self.i.o.ok)
 101         # CR0 to be set
 102         comb += self.o.cr0.data.eq(cr0)
 103         comb += self.o.cr0.ok.eq(op.write_cr0)
 104         # context
 105         comb += self.o.ctx.eq(self.i.ctx)
 106
 107         return m