src/soc/fu/common_output_stage.py

   1 # This stage is intended to handle the gating of carry out,
   2 # and updating the condition register
   3 from nmigen import (Module, Signal, Cat)
   4 from nmutil.pipemodbase import PipeModBase
   5 from ieee754.part.partsig import PartitionedSignal
   6 from soc.decoder.power_enums import InternalOp
   7
   8
   9 class CommonOutputStage(PipeModBase):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "output")
  12
  13     def elaborate(self, platform):
  14         m = Module()
  15         comb = m.d.comb
  16         op = self.i.ctx.op
  17
  18         # op requests inversion of the output...
  19         o = Signal.like(self.i.o)
  20         if hasattr(op, "invert_out"): # ... optionally
  21             with m.If(op.invert_out):
  22                 comb += o.eq(~self.i.o.data)
  23             with m.Else():
  24                 comb += o.eq(self.i.o.data)
  25         else:
  26             comb += o.eq(self.i.o.data) # ... no inversion
  27
  28         # target register if 32-bit is only the 32 LSBs
  29         target = Signal(64, reset_less=True)
  30         with m.If(op.is_32bit):
  31             comb += target.eq(o[:32])
  32         with m.Else():
  33             comb += target.eq(o)
  34
  35         # Handle carry_out
  36         comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
  37         comb += self.o.xer_ca.ok.eq(op.output_carry)
  38
  39         # create condition register cr0 and sticky-overflow
  40         is_nzero = Signal(reset_less=True)
  41         is_positive = Signal(reset_less=True)
  42         is_negative = Signal(reset_less=True)
  43         msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
  44         is_cmp = Signal(reset_less=True)     # true if OP=CMP
  45         is_cmpeqb = Signal(reset_less=True)  # true if OP=CMPEQB
  46         self.so = Signal(1, reset_less=True)
  47         cr0 = Signal(4, reset_less=True)
  48
  49         # TODO: if o[63] is XORed with "operand == OP_CMP"
  50         # that can be used as a test of whether to invert the +ve/-ve test
  51         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
  52
  53         comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
  54         comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
  55         comb += msb_test.eq(target[-1] ^ is_cmp)
  56         comb += is_nzero.eq(target.bool())
  57         comb += is_positive.eq(is_nzero & ~msb_test)
  58         comb += is_negative.eq(is_nzero & msb_test)
  59
  60         with m.If(is_cmpeqb):
  61             comb += cr0.eq(self.i.cr0.data)
  62         with m.Else():
  63             comb += cr0.eq(Cat(self.so, ~is_nzero, is_positive, is_negative))
  64
  65         # copy out [inverted?] output, cr0, and context out
  66         comb += self.o.o.data.eq(o)
  67         comb += self.o.o.ok.eq(self.i.o.ok)
  68         # CR0 to be set
  69         comb += self.o.cr0.data.eq(cr0)
  70         comb += self.o.cr0.ok.eq(op.write_cr0)
  71         # context
  72         comb += self.o.ctx.eq(self.i.ctx)
  73
  74         return m