src/soc/fu/common_output_stage.py

   1 # This stage is intended to handle the gating of carry out,
   2 # and updating the condition register
   3 from nmigen import (Module, Signal, Cat, Repl)
   4 from nmutil.pipemodbase import PipeModBase
   5 from ieee754.part.partsig import PartitionedSignal
   6 from soc.decoder.power_enums import InternalOp
   7
   8
   9 class CommonOutputStage(PipeModBase):
  10     def __init__(self, pspec):
  11         super().__init__(pspec, "output")
  12
  13     def elaborate(self, platform):
  14         m = Module()
  15         comb = m.d.comb
  16         op = self.i.ctx.op
  17
  18         # op requests inversion of the output
  19         o = Signal.like(self.i.o)
  20         with m.If(op.invert_out):
  21             comb += o.eq(~self.i.o.data)
  22         with m.Else():
  23             comb += o.eq(self.i.o.data)
  24
  25         # target register if 32-bit is only the 32 LSBs
  26         target = Signal(64, reset_less=True)
  27         with m.If(op.is_32bit):
  28             comb += target.eq(o[:32])
  29         with m.Else():
  30             comb += target.eq(o)
  31
  32         # Handle carry_out
  33         comb += self.o.xer_ca.data.eq(self.i.xer_ca.data)
  34         comb += self.o.xer_ca.ok.eq(op.output_carry)
  35
  36         # create condition register cr0 and sticky-overflow
  37         is_nzero = Signal(reset_less=True)
  38         is_positive = Signal(reset_less=True)
  39         is_negative = Signal(reset_less=True)
  40         msb_test = Signal(reset_less=True) # set equal to MSB, invert if OP=CMP
  41         is_cmp = Signal(reset_less=True)   # true if OP=CMP
  42         is_cmpeqb = Signal(reset_less=True)   # true if OP=CMP
  43         self.so = Signal(1, reset_less=True)
  44         cr0 = Signal(4, reset_less=True)
  45
  46         # TODO: if o[63] is XORed with "operand == OP_CMP"
  47         # that can be used as a test of whether to invert the +ve/-ve test
  48         # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
  49
  50         comb += is_cmp.eq(op.insn_type == InternalOp.OP_CMP)
  51         comb += is_cmpeqb.eq(op.insn_type == InternalOp.OP_CMPEQB)
  52         comb += msb_test.eq(target[-1] ^ is_cmp)
  53         comb += is_nzero.eq(target.bool())
  54         comb += is_positive.eq(is_nzero & ~msb_test)
  55         comb += is_negative.eq(is_nzero & msb_test)
  56
  57         with m.If(is_cmpeqb):
  58             comb += cr0.eq(self.i.cr0.data)
  59         with m.Else():
  60             comb += cr0.eq(Cat(self.so, ~is_nzero, is_positive, is_negative))
  61
  62         # copy out [inverted] cr0, output, and context out
  63         comb += self.o.o.data.eq(o)
  64         comb += self.o.o.ok.eq(self.i.o.ok)
  65         comb += self.o.cr0.data.eq(cr0)
  66         comb += self.o.cr0.ok.eq(op.write_cr.ok)
  67         # CR0 to be set
  68         comb += self.o.ctx.eq(self.i.ctx)
  69
  70         return m