1 # This stage is intended to handle the gating of carry out,
2 # and updating the condition register
3 from nmigen
import (Module
, Signal
, Cat
)
4 from nmutil
.pipemodbase
import PipeModBase
5 from ieee754
.part
.partsig
import PartitionedSignal
6 from soc
.decoder
.power_enums
import InternalOp
9 class CommonOutputStage(PipeModBase
):
10 def __init__(self
, pspec
):
11 super().__init
__(pspec
, "output")
13 def elaborate(self
, platform
):
18 # op requests inversion of the output...
19 o
= Signal
.like(self
.i
.o
)
20 if hasattr(op
, "invert_out"): # ... optionally
21 with m
.If(op
.invert_out
):
22 comb
+= o
.eq(~self
.i
.o
.data
)
24 comb
+= o
.eq(self
.i
.o
.data
)
26 comb
+= o
.eq(self
.i
.o
.data
) # ... no inversion
28 # target register if 32-bit is only the 32 LSBs
29 # XXX ah. right. this needs to be done only if the *mode* is 32-bit
30 # see https://bugs.libre-soc.org/show_bug.cgi?id=424
31 target
= Signal(64, reset_less
=True)
32 #with m.If(op.is_32bit):
33 # comb += target.eq(o[:32])
35 # comb += target.eq(o)
38 # carry-out only if actually present in this input spec
39 # (note: MUL and DIV do not have it, but ALU and Logical do)
40 if hasattr(self
.i
, "xer_ca"):
42 comb
+= self
.o
.xer_ca
.data
.eq(self
.i
.xer_ca
.data
)
43 comb
+= self
.o
.xer_ca
.ok
.eq(op
.output_carry
)
45 # create condition register cr0 and sticky-overflow
46 is_nzero
= Signal(reset_less
=True)
47 is_positive
= Signal(reset_less
=True)
48 is_negative
= Signal(reset_less
=True)
49 msb_test
= Signal(reset_less
=True) # set equal to MSB, invert if OP=CMP
50 is_cmp
= Signal(reset_less
=True) # true if OP=CMP
51 is_cmpeqb
= Signal(reset_less
=True) # true if OP=CMPEQB
52 self
.so
= Signal(1, reset_less
=True)
53 cr0
= Signal(4, reset_less
=True)
55 # TODO: if o[63] is XORed with "operand == OP_CMP"
56 # that can be used as a test of whether to invert the +ve/-ve test
57 # see https://bugs.libre-soc.org/show_bug.cgi?id=305#c60
59 comb
+= is_cmp
.eq(op
.insn_type
== InternalOp
.OP_CMP
)
60 comb
+= is_cmpeqb
.eq(op
.insn_type
== InternalOp
.OP_CMPEQB
)
61 # nope - if *processor* mode is 32-bit
62 #with m.If(op.is_32bit):
63 # comb += msb_test.eq(target[-1] ^ is_cmp) # 64-bit MSB
65 # comb += msb_test.eq(target[31] ^ is_cmp) # 32-bit MSB
66 comb
+= msb_test
.eq(target
[-1]) # 64-bit MSB
67 comb
+= is_nzero
.eq(target
.bool())
68 with m
.If(is_cmp
): # invert pos/neg tests
69 comb
+= is_positive
.eq(msb_test
)
70 comb
+= is_negative
.eq(is_nzero
& ~msb_test
)
72 comb
+= is_negative
.eq(msb_test
)
73 comb
+= is_positive
.eq(is_nzero
& ~msb_test
)
76 comb
+= cr0
.eq(self
.i
.cr0
.data
)
78 comb
+= cr0
.eq(Cat(self
.so
, ~is_nzero
, is_positive
, is_negative
))
80 # copy out [inverted?] output, cr0, and context out
81 comb
+= self
.o
.o
.data
.eq(o
)
82 comb
+= self
.o
.o
.ok
.eq(self
.i
.o
.ok
)
84 comb
+= self
.o
.cr0
.data
.eq(cr0
)
85 comb
+= self
.o
.cr0
.ok
.eq(op
.write_cr0
)
87 comb
+= self
.o
.ctx
.eq(self
.i
.ctx
)