src/soc/fu/compunits/formal/test_compunit.py

   1 from nmigen import Signal, Module
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 from soc.fu.compunits.compunits import FunctionUnitBaseSingle
   6 from soc.experiment.alu_hier import DummyALU
   7 from soc.experiment.compalu_multi import MultiCompUnit
   8 from soc.fu.alu.alu_input_record import CompALUOpSubset
   9 from soc.decoder.power_enums import InternalOp
  10 import unittest
  11
  12 class MaskGenTestCase(FHDLTestCase):
  13     def test_maskgen(self):
  14         m = Module()
  15         comb = m.d.comb
  16         alu = DummyALU(16)
  17         m.submodules.dut = dut = MultiCompUnit(16, alu,
  18                                                CompALUOpSubset)
  19         sim = Simulator(m)
  20
  21         def process():
  22             yield dut.src1_i.eq(0x5)
  23             yield dut.src2_i.eq(0x5)
  24             yield dut.issue_i.eq(1)
  25             yield dut.oper_i.insn_type.eq(InternalOp.OP_ADD)
  26             yield
  27             yield dut.issue_i.eq(0)
  28             yield
  29             while True:
  30                 yield
  31                 rd_rel = yield dut.rd.rel
  32                 if rd_rel != 0:
  33                     break
  34             yield dut.rd.go.eq(0xfff)
  35             yield
  36             yield dut.rd.go.eq(0)
  37             for i in range(10):
  38                 yield
  39
  40
  41
  42         sim.add_clock(1e-6)
  43         sim.add_sync_process(process)
  44         with sim.write_vcd("compunit.vcd", "compunit.gtkw", traces=dut.ports()):
  45             sim.run()
  46
  47 if __name__ == '__main__':
  48     unittest.main()