src/soc/fu/compunits/test/test_alu_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.alu.test.test_pipe_caller import ALUTestCase # creates the tests
   6 from soc.fu.alu.test.test_pipe_caller import test_data # imports the data
   7
   8 from soc.fu.compunits.compunits import ALUFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11
  12 class ALUTestRunner(TestRunner):
  13     def __init__(self, test_data):
  14         super().__init__(test_data, ALUFunctionUnit, self,
  15                          Function.ALU)
  16
  17     def get_cu_inputs(self, dec2, sim):
  18         """naming (res) must conform to ALUFunctionUnit input regspec
  19         """
  20         res = {}
  21
  22         # RA (or RC)
  23         reg1_ok = yield dec2.e.read_reg1.ok
  24         if reg1_ok:
  25             data1 = yield dec2.e.read_reg1.data
  26             res['a'] = sim.gpr(data1).value
  27
  28         # RB (or immediate)
  29         reg2_ok = yield dec2.e.read_reg2.ok
  30         if reg2_ok:
  31             data2 = yield dec2.e.read_reg2.data
  32             res['b'] = sim.gpr(data2).value
  33
  34         # XER.ca
  35         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  36         carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  37         res['xer_ca'] = carry | (carry32<<1)
  38
  39         # XER.so
  40         so = 1 if sim.spr['XER'][XER_bits['SO']] else 0
  41         res['xer_so'] = so
  42
  43         return res
  44
  45     def check_cu_outputs(self, res, dec2, sim, code):
  46         """naming (res) must conform to ALUFunctionUnit output regspec
  47         """
  48
  49         # RT
  50         out_reg_valid = yield dec2.e.write_reg.ok
  51         if out_reg_valid:
  52             write_reg_idx = yield dec2.e.write_reg.data
  53             expected = sim.gpr(write_reg_idx).value
  54             cu_out = res['o']
  55             print(f"expected {expected:x}, actual: {cu_out:x}")
  56             self.assertEqual(expected, cu_out, code)
  57
  58         rc = yield dec2.e.rc.data
  59         op = yield dec2.e.insn_type
  60         cridx_ok = yield dec2.e.write_cr.ok
  61         cridx = yield dec2.e.write_cr.data
  62
  63         print ("check extra output", repr(code), cridx_ok, cridx)
  64
  65         if rc:
  66             self.assertEqual(cridx_ok, 1, code)
  67             self.assertEqual(cridx, 0, code)
  68
  69         # CR (CR0-7)
  70         if cridx_ok:
  71             cr_expected = sim.crl[cridx].get_range().value
  72             cr_actual = res['cr0']
  73             print ("CR", cridx, cr_expected, cr_actual)
  74             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  75
  76         # XER.ca
  77         cry_out = yield dec2.e.output_carry
  78         if cry_out:
  79             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  80             xer_ca = res['xer_ca']
  81             real_carry = xer_ca & 0b1 # XXX CO not CO32
  82             self.assertEqual(expected_carry, real_carry, code)
  83             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  84             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  85             self.assertEqual(expected_carry32, real_carry32, code)
  86
  87         # TODO: XER.ov and XER.so
  88         oe = yield dec2.e.oe.data
  89         if oe:
  90             xer_ov = res['xer_ov']
  91             xer_so = res['xer_so']
  92
  93
  94 if __name__ == "__main__":
  95     unittest.main(exit=False)
  96     suite = unittest.TestSuite()
  97     suite.addTest(ALUTestRunner(test_data))
  98
  99     runner = unittest.TextTestRunner()
 100     runner.run(suite)