1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
14 from soc
.fu
.alu
.test
.test_pipe_caller
import TestCase
, ALUTestCase
, test_data
15 from soc
.fu
.compunits
.compunits
import ALUFunctionUnit
16 from soc
.experiment
.compalu_multi
import find_ok
# hack
19 def set_cu_input(cu
, idx
, data
):
20 yield cu
.src_i
[idx
].eq(data
)
22 rd_rel_o
= yield cu
.rd
.rel
[idx
]
23 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
27 yield cu
.rd
.go
[idx
].eq(1)
30 rd_rel_o
= yield cu
.rd
.rel
[idx
]
33 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
35 yield cu
.rd
.go
[idx
].eq(0)
38 def get_cu_output(cu
, idx
, code
):
39 wrmask
= yield cu
.wrmask
40 wrop
= cu
.get_out_name(idx
)
41 wrok
= cu
.get_out(idx
)
42 fname
= find_ok(wrok
.fields
)
43 wrok
= yield getattr(wrok
, fname
)
44 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
45 assert wrmask
& (1<<idx
), \
46 "get_cu_output '%s': mask bit %d not set\n" \
47 "write-operand '%s' Data.ok likely not set (%s)" \
48 % (code
, idx
, wrop
, hex(wrok
))
50 wr_relall_o
= yield cu
.wr
.rel
51 wr_rel_o
= yield cu
.wr
.rel
[idx
]
52 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
56 yield cu
.wr
.go
[idx
].eq(1)
58 result
= yield cu
.dest
[idx
]
59 yield cu
.wr
.go
[idx
].eq(0)
63 def get_cu_rd_mask(dec2
):
65 mask
= 0b1100 # XER CA/SO
67 reg3_ok
= yield dec2
.e
.read_reg3
.ok
68 reg1_ok
= yield dec2
.e
.read_reg1
.ok
70 if reg3_ok
or reg1_ok
:
73 # If there's an immediate, set the B operand to that
74 reg2_ok
= yield dec2
.e
.read_reg2
.ok
81 def set_cu_inputs(cu
, dec2
, sim
):
82 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
83 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
84 # and place it into data_i.b
86 reg3_ok
= yield dec2
.e
.read_reg3
.ok
87 reg1_ok
= yield dec2
.e
.read_reg1
.ok
88 assert reg3_ok
!= reg1_ok
90 data1
= yield dec2
.e
.read_reg3
.data
91 data1
= sim
.gpr(data1
).value
93 data1
= yield dec2
.e
.read_reg1
.data
94 data1
= sim
.gpr(data1
).value
98 if reg3_ok
or reg1_ok
:
99 yield from set_cu_input(cu
, 0, data1
)
101 # If there's an immediate, set the B operand to that
102 reg2_ok
= yield dec2
.e
.read_reg2
.ok
104 data2
= yield dec2
.e
.read_reg2
.data
105 data2
= sim
.gpr(data2
).value
110 yield from set_cu_input(cu
, 1, data2
)
113 def set_operand(cu
, dec2
, sim
):
114 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
115 yield cu
.issue_i
.eq(1)
117 yield cu
.issue_i
.eq(0)
121 def set_extra_cu_inputs(cu
, dec2
, sim
):
122 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
123 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
124 yield from set_cu_input(cu
, 3, carry |
(carry32
<<1))
125 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
126 yield from set_cu_input(cu
, 2, so
)
130 class TestRunner(FHDLTestCase
):
131 def __init__(self
, test_data
):
132 super().__init
__("run_all")
133 self
.test_data
= test_data
138 instruction
= Signal(32)
140 pdecode
= create_pdecode()
142 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
143 m
.submodules
.cu
= cu
= ALUFunctionUnit()
145 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
151 yield cu
.issue_i
.eq(0)
154 for test
in self
.test_data
:
156 program
= test
.program
157 self
.subTest(test
.name
)
158 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
159 gen
= program
.generate_instructions()
160 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
162 index
= sim
.pc
.CIA
.value
//4
163 while index
< len(instructions
):
164 ins
, code
= instructions
[index
]
166 print("0x{:X}".format(ins
& 0xffffffff))
169 # ask the decoder to decode this binary data (endian'd)
170 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
171 yield instruction
.eq(ins
) # raw binary instr.
173 fn_unit
= yield pdecode2
.e
.fn_unit
174 self
.assertEqual(fn_unit
, Function
.ALU
.value
)
175 # reset read-operand mask
176 rdmask
= yield from get_cu_rd_mask(pdecode2
)
177 yield cu
.rdmaskn
.eq(~rdmask
)
178 yield from set_operand(cu
, pdecode2
, sim
)
179 rd_rel_o
= yield cu
.rd
.rel
180 wr_rel_o
= yield cu
.wr
.rel
181 print ("before inputs, rd_rel, wr_rel: ",
182 bin(rd_rel_o
), bin(wr_rel_o
))
183 yield from set_cu_inputs(cu
, pdecode2
, sim
)
184 yield from set_extra_cu_inputs(cu
, pdecode2
, sim
)
186 rd_rel_o
= yield cu
.rd
.rel
187 wr_rel_o
= yield cu
.wr
.rel
188 wrmask
= yield cu
.wrmask
189 print ("after inputs, rd_rel, wr_rel, wrmask: ",
190 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
191 opname
= code
.split(' ')[0]
192 yield from sim
.call(opname
)
193 index
= sim
.pc
.CIA
.value
//4
195 out_reg_valid
= yield pdecode2
.e
.write_reg
.ok
200 write_reg_idx
= yield pdecode2
.e
.write_reg
.data
201 expected
= sim
.gpr(write_reg_idx
).value
202 cu_out
= yield from get_cu_output(cu
, 0, code
)
203 print(f
"expected {expected:x}, actual: {cu_out:x}")
204 self
.assertEqual(expected
, cu_out
, code
)
208 yield from self
.check_extra_cu_outputs(cu
, pdecode2
,
212 busy_o
= yield cu
.busy_o
214 for i
in range(cu
.n_dst
):
215 wr_rel_o
= yield cu
.wr
.rel
[i
]
217 print ("discard output", i
)
218 discard
= yield from get_cu_output(cu
, i
, code
)
221 sim
.add_sync_process(process
)
222 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
226 def check_extra_cu_outputs(self
, cu
, dec2
, sim
, code
):
227 rc
= yield dec2
.e
.rc
.data
228 op
= yield dec2
.e
.insn_type
231 op
== InternalOp
.OP_CMP
.value
or \
232 op
== InternalOp
.OP_CMPEQB
.value
:
233 cr_actual
= yield from get_cu_output(cu
, 1, code
)
236 cr_expected
= sim
.crl
[0].get_range().value
237 self
.assertEqual(cr_expected
, cr_actual
, code
)
239 if op
== InternalOp
.OP_CMP
.value
or \
240 op
== InternalOp
.OP_CMPEQB
.value
:
241 bf
= yield dec2
.dec
.BF
242 cr_expected
= sim
.crl
[bf
].get_range().value
243 self
.assertEqual(cr_expected
, cr_actual
, code
)
245 cry_out
= yield dec2
.e
.output_carry
247 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
248 xer_ca
= yield from get_cu_output(cu
, 2, code
)
249 real_carry
= xer_ca
& 0b1 # XXX CO not CO32
250 self
.assertEqual(expected_carry
, real_carry
, code
)
251 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
252 real_carry32
= bool(xer_ca
& 0b10) # XXX CO32
253 self
.assertEqual(expected_carry32
, real_carry32
, code
)
255 xer_ov
= yield from get_cu_output(cu
, 3, code
)
256 xer_so
= yield from get_cu_output(cu
, 4, code
)
259 if __name__
== "__main__":
260 unittest
.main(exit
=False)
261 suite
= unittest
.TestSuite()
262 suite
.addTest(TestRunner(test_data
))
264 runner
= unittest
.TextTestRunner()