2 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
4 # XXX bad practice: use of global variables
5 from soc
.fu
.alu
.test
.test_pipe_caller
import ALUTestCase
# creates the tests
6 from soc
.fu
.alu
.test
.test_pipe_caller
import test_data
# imports the data
8 from soc
.fu
.compunits
.compunits
import ALUFunctionUnit
9 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
12 class ALUTestRunner(TestRunner
):
13 def __init__(self
, test_data
):
14 super().__init
__(test_data
, ALUFunctionUnit
, self
,
17 def get_cu_inputs(self
, dec2
, sim
):
18 """naming (res) must conform to ALUFunctionUnit input regspec
23 reg3_ok
= yield dec2
.e
.read_reg3
.ok
24 reg1_ok
= yield dec2
.e
.read_reg1
.ok
25 assert reg3_ok
!= reg1_ok
27 data1
= yield dec2
.e
.read_reg3
.data
28 res
['a'] = sim
.gpr(data1
).value
30 data1
= yield dec2
.e
.read_reg1
.data
31 res
['a'] = sim
.gpr(data1
).value
34 reg2_ok
= yield dec2
.e
.read_reg2
.ok
36 data2
= yield dec2
.e
.read_reg2
.data
37 res
['b'] = sim
.gpr(data2
).value
40 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
41 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
42 res
['xer_ca'] = carry |
(carry32
<<1)
45 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
50 def check_cu_outputs(self
, res
, dec2
, sim
, code
):
51 """naming (res) must conform to ALUFunctionUnit output regspec
55 out_reg_valid
= yield dec2
.e
.write_reg
.ok
57 write_reg_idx
= yield dec2
.e
.write_reg
.data
58 expected
= sim
.gpr(write_reg_idx
).value
60 print(f
"expected {expected:x}, actual: {cu_out:x}")
61 self
.assertEqual(expected
, cu_out
, code
)
63 rc
= yield dec2
.e
.rc
.data
64 op
= yield dec2
.e
.insn_type
65 cridx_ok
= yield dec2
.e
.write_cr
.ok
66 cridx
= yield dec2
.e
.write_cr
.data
68 print ("check extra output", repr(code
), cridx_ok
, cridx
)
71 self
.assertEqual(cridx_ok
, 1, code
)
72 self
.assertEqual(cridx
, 0, code
)
76 cr_expected
= sim
.crl
[cridx
].get_range().value
77 cr_actual
= res
['cr0']
78 print ("CR", cridx
, cr_expected
, cr_actual
)
79 self
.assertEqual(cr_expected
, cr_actual
, "CR%d %s" % (cridx
, code
))
82 cry_out
= yield dec2
.e
.output_carry
84 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
85 xer_ca
= res
['xer_ca']
86 real_carry
= xer_ca
& 0b1 # XXX CO not CO32
87 self
.assertEqual(expected_carry
, real_carry
, code
)
88 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
89 real_carry32
= bool(xer_ca
& 0b10) # XXX CO32
90 self
.assertEqual(expected_carry32
, real_carry32
, code
)
92 # TODO: XER.ov and XER.so
93 oe
= yield dec2
.e
.oe
.data
95 xer_ov
= res
['xer_ov']
96 xer_so
= res
['xer_so']
99 if __name__
== "__main__":
100 unittest
.main(exit
=False)
101 suite
= unittest
.TestSuite()
102 suite
.addTest(ALUTestRunner(test_data
))
104 runner
= unittest
.TextTestRunner()