1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
14 from soc
.fu
.alu
.test
.test_pipe_caller
import TestCase
, ALUTestCase
, test_data
15 from soc
.fu
.compunits
.compunits
import ALUFunctionUnit
18 def set_cu_input(cu
, idx
, data
):
19 yield cu
.src_i
[idx
].eq(data
)
21 rd_rel_o
= yield cu
.rd
.rel
[idx
]
22 print ("rd_rel %d wait" % idx
, rd_rel_o
)
26 yield cu
.rd
.go
[idx
].eq(1)
28 yield cu
.rd
.go
[idx
].eq(0)
31 def get_cu_output(cu
, idx
):
33 wr_relall_o
= yield cu
.wr
.rel
34 wr_rel_o
= yield cu
.wr
.rel
[idx
]
35 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
39 yield cu
.wr
.go
[idx
].eq(1)
41 result
= yield cu
.dst_i
[idx
]
42 yield cu
.wr
.go
[idx
].eq(0)
46 def set_cu_inputs(cu
, dec2
, sim
):
47 # TODO: see https://bugs.libre-soc.org/show_bug.cgi?id=305#c43
48 # detect the immediate here (with m.If(self.i.ctx.op.imm_data.imm_ok))
49 # and place it into data_i.b
51 reg3_ok
= yield dec2
.e
.read_reg3
.ok
52 reg1_ok
= yield dec2
.e
.read_reg1
.ok
53 assert reg3_ok
!= reg1_ok
55 data1
= yield dec2
.e
.read_reg3
.data
56 data1
= sim
.gpr(data1
).value
58 data1
= yield dec2
.e
.read_reg1
.data
59 data1
= sim
.gpr(data1
).value
63 if reg3_ok
or reg1_ok
:
64 yield from set_cu_input(cu
, 0, data1
)
66 # If there's an immediate, set the B operand to that
67 reg2_ok
= yield dec2
.e
.read_reg2
.ok
69 data2
= yield dec2
.e
.read_reg2
.data
70 data2
= sim
.gpr(data2
).value
75 yield from set_cu_input(cu
, 1, data2
)
78 def set_operand(cu
, dec2
, sim
):
79 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
80 yield cu
.issue_i
.eq(1)
82 yield cu
.issue_i
.eq(0)
86 def set_extra_cu_inputs(cu
, dec2
, sim
):
87 carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
88 carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
89 yield from set_cu_input(cu
, 2, carry |
(carry32
<<1))
90 so
= 1 if sim
.spr
['XER'][XER_bits
['SO']] else 0
91 yield from set_cu_input(cu
, 3, so
)
95 class TestRunner(FHDLTestCase
):
96 def __init__(self
, test_data
):
97 super().__init
__("run_all")
98 self
.test_data
= test_data
103 instruction
= Signal(32)
105 pdecode
= create_pdecode()
107 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
108 m
.submodules
.cu
= cu
= ALUFunctionUnit()
110 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
115 for test
in self
.test_data
:
117 program
= test
.program
118 self
.subTest(test
.name
)
119 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
120 gen
= program
.generate_instructions()
121 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
123 index
= sim
.pc
.CIA
.value
//4
124 while index
< len(instructions
):
125 ins
, code
= instructions
[index
]
127 print("0x{:X}".format(ins
& 0xffffffff))
130 # ask the decoder to decode this binary data (endian'd)
131 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
132 yield instruction
.eq(ins
) # raw binary instr.
134 fn_unit
= yield pdecode2
.e
.fn_unit
135 self
.assertEqual(fn_unit
, Function
.ALU
.value
)
136 yield from set_operand(cu
, pdecode2
, sim
)
137 yield from set_cu_inputs(cu
, pdecode2
, sim
)
138 yield from set_extra_cu_inputs(cu
, pdecode2
, sim
)
140 opname
= code
.split(' ')[0]
141 yield from sim
.call(opname
)
142 index
= sim
.pc
.CIA
.value
//4
144 out_reg_valid
= yield pdecode2
.e
.write_reg
.ok
146 write_reg_idx
= yield pdecode2
.e
.write_reg
.data
147 expected
= sim
.gpr(write_reg_idx
).value
148 cu_out
= yield from get_cu_output(cu
, 0)
149 print(f
"expected {expected:x}, actual: {cu_out:x}")
150 self
.assertEqual(expected
, cu_out
, code
)
151 yield from self
.check_extra_cu_outputs(cu
, pdecode2
,
154 sim
.add_sync_process(process
)
155 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",
159 def check_extra_cu_outputs(self
, cu
, dec2
, sim
, code
):
160 rc
= yield dec2
.e
.rc
.data
162 cr_expected
= sim
.crl
[0].get_range().value
163 cr_actual
= yield cu
.n
.data_o
.cr0
.data
164 self
.assertEqual(cr_expected
, cr_actual
, code
)
166 op
= yield dec2
.e
.insn_type
167 if op
== InternalOp
.OP_CMP
.value
or \
168 op
== InternalOp
.OP_CMPEQB
.value
:
169 bf
= yield dec2
.dec
.BF
170 cr_actual
= yield cu
.n
.data_o
.cr0
.data
171 cr_expected
= sim
.crl
[bf
].get_range().value
172 self
.assertEqual(cr_expected
, cr_actual
, code
)
174 cry_out
= yield dec2
.e
.output_carry
176 expected_carry
= 1 if sim
.spr
['XER'][XER_bits
['CA']] else 0
177 real_carry
= yield cu
.n
.data_o
.xer_ca
.data
[0] # XXX CO not CO32
178 self
.assertEqual(expected_carry
, real_carry
, code
)
179 expected_carry32
= 1 if sim
.spr
['XER'][XER_bits
['CA32']] else 0
180 real_carry32
= yield cu
.n
.data_o
.xer_ca
.data
[1] # XXX CO32
181 self
.assertEqual(expected_carry32
, real_carry32
, code
)
185 if __name__
== "__main__":
186 unittest
.main(exit
=False)
187 suite
= unittest
.TestSuite()
188 suite
.addTest(TestRunner(test_data
))
190 runner
= unittest
.TextTestRunner()