135e6fe52e55e4f5855bc7673d1abf598b691999
1 from nmigen
import Module
, Signal
, ResetSignal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.decoder
.power_enums
import Function
9 from soc
.decoder
.isa
.all
import ISA
11 from soc
.experiment
.compalu_multi
import find_ok
# hack
12 from soc
.config
.test
.test_loadstore
import TestMemPspec
15 def set_cu_input(cu
, idx
, data
):
16 rdop
= cu
.get_in_name(idx
)
17 yield cu
.src_i
[idx
].eq(data
)
19 rd_rel_o
= yield cu
.rd
.rel
[idx
]
20 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
24 yield cu
.rd
.go
[idx
].eq(1)
27 rd_rel_o
= yield cu
.rd
.rel
[idx
]
30 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
32 yield cu
.rd
.go
[idx
].eq(0)
33 yield cu
.src_i
[idx
].eq(0)
36 def get_cu_output(cu
, idx
, code
):
37 wrmask
= yield cu
.wrmask
38 wrop
= cu
.get_out_name(idx
)
39 wrok
= cu
.get_out(idx
)
40 fname
= find_ok(wrok
.fields
)
41 wrok
= yield getattr(wrok
, fname
)
42 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
43 assert wrmask
& (1<<idx
), \
44 "get_cu_output '%s': mask bit %d not set\n" \
45 "write-operand '%s' Data.ok likely not set (%s)" \
46 % (code
, idx
, wrop
, hex(wrok
))
48 wr_relall_o
= yield cu
.wr
.rel
49 wr_rel_o
= yield cu
.wr
.rel
[idx
]
50 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
54 yield cu
.wr
.go
[idx
].eq(1)
56 result
= yield cu
.dest
[idx
]
58 yield cu
.wr
.go
[idx
].eq(0)
59 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
64 def set_cu_inputs(cu
, inp
):
65 print ("set_cu_inputs", inp
)
66 for idx
, data
in inp
.items():
67 yield from set_cu_input(cu
, idx
, data
)
68 # gets out of sync when checking busy if there is no wait, here.
70 yield # wait one cycle
74 def set_operand(cu
, dec2
, sim
):
75 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
76 yield cu
.issue_i
.eq(1)
78 yield cu
.issue_i
.eq(0)
82 def get_cu_outputs(cu
, code
):
84 wrmask
= yield cu
.wrmask
85 wr_rel_o
= yield cu
.wr
.rel
86 print ("get_cu_outputs", cu
.n_dst
, wrmask
, wr_rel_o
)
87 if not wrmask
: # no point waiting (however really should doublecheck wr.rel)
89 # wait for at least one result
91 wr_rel_o
= yield cu
.wr
.rel
95 for i
in range(cu
.n_dst
):
96 wr_rel_o
= yield cu
.wr
.rel
[i
]
98 result
= yield from get_cu_output(cu
, i
, code
)
99 wrop
= cu
.get_out_name(i
)
100 print ("output", i
, wrop
, hex(result
))
105 def get_inp_indexed(cu
, inp
):
107 for i
in range(cu
.n_src
):
108 wrop
= cu
.get_in_name(i
)
113 def get_l0_mem(l0
): # BLECH!
114 if hasattr(l0
.pimem
, 'lsui'):
115 return l0
.pimem
.lsui
.mem
116 return l0
.pimem
.mem
.mem
118 def setup_test_memory(l0
, sim
):
120 print ("before, init mem", mem
.depth
, mem
.width
, mem
)
121 for i
in range(mem
.depth
):
122 data
= sim
.mem
.ld(i
*8, 8, False)
123 print ("init ", i
, hex(data
))
124 yield mem
._array
[i
].eq(data
)
126 for k
, v
in sim
.mem
.mem
.items():
127 print (" %6x %016x" % (k
, v
))
128 print ("before, nmigen mem dump")
129 for i
in range(mem
.depth
):
130 actual_mem
= yield mem
._array
[i
]
131 print (" %6i %016x" % (i
, actual_mem
))
134 def dump_sim_memory(dut
, l0
, sim
, code
):
136 print ("sim mem dump")
137 for k
, v
in sim
.mem
.mem
.items():
138 print (" %6x %016x" % (k
, v
))
139 print ("nmigen mem dump")
140 for i
in range(mem
.depth
):
141 actual_mem
= yield mem
._array
[i
]
142 print (" %6i %016x" % (i
, actual_mem
))
145 def check_sim_memory(dut
, l0
, sim
, code
):
148 for i
in range(mem
.depth
):
149 expected_mem
= sim
.mem
.ld(i
*8, 8, False)
150 actual_mem
= yield mem
._array
[i
]
151 dut
.assertEqual(expected_mem
, actual_mem
,
152 "%s %d %x %x" % (code
, i
,
153 expected_mem
, actual_mem
))
155 class TestRunner(FHDLTestCase
):
156 def __init__(self
, test_data
, fukls
, iodef
, funit
, bigendian
):
157 super().__init
__("run_all")
158 self
.test_data
= test_data
162 self
.bigendian
= bigendian
167 instruction
= Signal(32)
169 pdecode
= create_pdecode()
170 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
172 # copy of the decoder for simulator
173 simdec
= create_pdecode()
174 simdec2
= PowerDecode2(simdec
)
175 m
.submodules
.simdec2
= simdec2
# pain in the neck
177 if self
.funit
== Function
.LDST
:
178 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
179 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
183 m
.submodules
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
185 m
.submodules
.cu
= cu
= self
.fukls(pi
, idx
=0, awid
=3)
186 m
.d
.comb
+= cu
.ad
.go
.eq(cu
.ad
.rel
) # link addr-go direct to rel
187 m
.d
.comb
+= cu
.st
.go
.eq(cu
.st
.rel
) # link store-go direct to rel
189 m
.submodules
.cu
= cu
= self
.fukls(0)
191 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
197 yield cu
.issue_i
.eq(0)
200 for test
in self
.test_data
:
202 program
= test
.program
203 self
.subTest(test
.name
)
204 print ("test", test
.name
, test
.mem
)
205 gen
= list(program
.generate_instructions())
206 insncode
= program
.assembly
.splitlines()
207 instructions
= list(zip(gen
, insncode
))
208 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
210 initial_insns
=gen
, respect_pc
=True,
211 disassembly
=insncode
,
212 bigendian
=self
.bigendian
)
215 if self
.funit
== Function
.LDST
:
216 yield from setup_test_memory(l0
, sim
)
218 pc
= sim
.pc
.CIA
.value
222 print("instr pc", pc
)
224 yield from sim
.setup_one()
225 except KeyError: # indicates instruction not in imem: stop
228 ins
, code
= instructions
[index
]
229 print("instruction @", index
, code
)
231 # ask the decoder to decode this binary data (endian'd)
232 yield pdecode2
.dec
.bigendian
.eq(self
.bigendian
) # le / be?
233 yield pdecode2
.msr
.eq(msr
) # set MSR "state"
234 yield pdecode2
.cia
.eq(pc
) # set PC "state"
235 yield instruction
.eq(ins
) # raw binary instr.
237 # debugging issue with branch
238 if self
.funit
== Function
.BRANCH
:
239 lk
= yield pdecode2
.e
.do
.lk
240 fast_out2
= yield pdecode2
.e
.write_fast2
.data
241 fast_out2_ok
= yield pdecode2
.e
.write_fast2
.ok
242 print ("lk:", lk
, fast_out2
, fast_out2_ok
)
243 op_lk
= yield cu
.alu
.pipe1
.p
.data_i
.ctx
.op
.lk
244 print ("op_lk:", op_lk
)
245 print (dir(cu
.alu
.pipe1
.n
.data_o
))
246 fn_unit
= yield pdecode2
.e
.do
.fn_unit
247 fuval
= self
.funit
.value
248 self
.assertEqual(fn_unit
& fuval
, fuval
)
250 # set operand and get inputs
251 yield from set_operand(cu
, pdecode2
, sim
)
252 # reset read-operand mask
253 rdmask
= pdecode2
.rdflags(cu
)
254 #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
255 #print ("decoder rdmask", rdmask)
256 yield cu
.rdmaskn
.eq(~rdmask
)
259 iname
= yield from self
.iodef
.get_cu_inputs(pdecode2
, sim
)
260 inp
= get_inp_indexed(cu
, iname
)
262 # reset write-operand mask
263 for idx
in range(cu
.n_dst
):
264 wrok
= cu
.get_out(idx
)
265 fname
= find_ok(wrok
.fields
)
266 yield getattr(wrok
, fname
).eq(0)
271 rd_rel_o
= yield cu
.rd
.rel
272 wr_rel_o
= yield cu
.wr
.rel
273 print ("before inputs, rd_rel, wr_rel: ",
274 bin(rd_rel_o
), bin(wr_rel_o
))
275 assert wr_rel_o
== 0, "wr.rel %s must be zero. "\
276 "previous instr not written all regs\n"\
278 (bin(wr_rel_o
), cu
.rwid
[1])
279 yield from set_cu_inputs(cu
, inp
)
280 rd_rel_o
= yield cu
.rd
.rel
281 wr_rel_o
= yield cu
.wr
.rel
282 wrmask
= yield cu
.wrmask
283 print ("after inputs, rd_rel, wr_rel, wrmask: ",
284 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
286 # call simulated operation
287 yield from sim
.execute_one()
289 pc
= sim
.pc
.CIA
.value
293 # get all outputs (one by one, just "because")
294 res
= yield from get_cu_outputs(cu
, code
)
295 wrmask
= yield cu
.wrmask
296 rd_rel_o
= yield cu
.rd
.rel
297 wr_rel_o
= yield cu
.wr
.rel
298 print ("after got outputs, rd_rel, wr_rel, wrmask: ",
299 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
301 # reset read-mask. IMPORTANT when there are no operands
302 yield cu
.rdmaskn
.eq(0)
304 # wait for busy to go low
306 busy_o
= yield cu
.busy_o
307 print ("busy", busy_o
)
313 # debugging issue with branch
314 if self
.funit
== Function
.BRANCH
:
315 lr
= yield cu
.alu
.pipe1
.n
.data_o
.lr
.data
316 lr_ok
= yield cu
.alu
.pipe1
.n
.data_o
.lr
.ok
317 print ("lr:", hex(lr
), lr_ok
)
319 if self
.funit
== Function
.LDST
:
320 yield from dump_sim_memory(self
, l0
, sim
, code
)
323 # sigh. hard-coded. test memory
324 if self
.funit
== Function
.LDST
:
325 yield from check_sim_memory(self
, l0
, sim
, code
)
326 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
330 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
335 sim
.add_sync_process(process
)
337 name
= self
.funit
.name
.lower()
338 with sim
.write_vcd("%s_simulator.vcd" % name
,