1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
14 from soc
.fu
.alu
.test
.test_pipe_caller
import TestCase
, ALUTestCase
, test_data
15 from soc
.experiment
.compalu_multi
import find_ok
# hack
19 def set_cu_input(cu
, idx
, data
):
20 rdop
= cu
.get_in_name(idx
)
21 yield cu
.src_i
[idx
].eq(data
)
23 rd_rel_o
= yield cu
.rd
.rel
[idx
]
24 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
28 yield cu
.rd
.go
[idx
].eq(1)
31 rd_rel_o
= yield cu
.rd
.rel
[idx
]
34 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
36 yield cu
.rd
.go
[idx
].eq(0)
37 yield cu
.src_i
[idx
].eq(0)
40 def get_cu_output(cu
, idx
, code
):
41 wrmask
= yield cu
.wrmask
42 wrop
= cu
.get_out_name(idx
)
43 wrok
= cu
.get_out(idx
)
44 fname
= find_ok(wrok
.fields
)
45 wrok
= yield getattr(wrok
, fname
)
46 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
47 assert wrmask
& (1<<idx
), \
48 "get_cu_output '%s': mask bit %d not set\n" \
49 "write-operand '%s' Data.ok likely not set (%s)" \
50 % (code
, idx
, wrop
, hex(wrok
))
52 wr_relall_o
= yield cu
.wr
.rel
53 wr_rel_o
= yield cu
.wr
.rel
[idx
]
54 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
58 yield cu
.wr
.go
[idx
].eq(1)
60 result
= yield cu
.dest
[idx
]
62 yield cu
.wr
.go
[idx
].eq(0)
63 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
67 def set_cu_inputs(cu
, inp
):
68 for idx
, data
in inp
.items():
69 yield from set_cu_input(cu
, idx
, data
)
72 def set_operand(cu
, dec2
, sim
):
73 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
74 yield cu
.issue_i
.eq(1)
76 yield cu
.issue_i
.eq(0)
80 def get_cu_outputs(cu
, code
):
82 for i
in range(cu
.n_dst
):
83 wr_rel_o
= yield cu
.wr
.rel
[i
]
85 result
= yield from get_cu_output(cu
, i
, code
)
86 wrop
= cu
.get_out_name(i
)
87 print ("output", i
, wrop
, hex(result
))
92 def get_inp_indexed(cu
, inp
):
94 for i
in range(cu
.n_src
):
95 wrop
= cu
.get_in_name(i
)
101 class TestRunner(FHDLTestCase
):
102 def __init__(self
, test_data
, fukls
, iodef
, funit
):
103 super().__init
__("run_all")
104 self
.test_data
= test_data
112 instruction
= Signal(32)
114 pdecode
= create_pdecode()
116 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
117 m
.submodules
.cu
= cu
= self
.fukls()
119 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
125 yield cu
.issue_i
.eq(0)
128 for test
in self
.test_data
:
130 program
= test
.program
131 self
.subTest(test
.name
)
132 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
133 gen
= program
.generate_instructions()
134 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
136 index
= sim
.pc
.CIA
.value
//4
137 while index
< len(instructions
):
138 ins
, code
= instructions
[index
]
140 print("0x{:X}".format(ins
& 0xffffffff))
143 # ask the decoder to decode this binary data (endian'd)
144 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
145 yield instruction
.eq(ins
) # raw binary instr.
147 fn_unit
= yield pdecode2
.e
.fn_unit
148 fuval
= self
.funit
.value
149 self
.assertEqual(fn_unit
& fuval
, fuval
)
151 # set operand and get inputs
152 yield from set_operand(cu
, pdecode2
, sim
)
153 iname
= yield from self
.iodef
.get_cu_inputs(pdecode2
, sim
)
154 inp
= get_inp_indexed(cu
, iname
)
156 # reset read-operand mask
157 rdmask
= pdecode2
.rdflags(cu
)
158 #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
159 #print ("decoder rdmask", rdmask)
160 yield cu
.rdmaskn
.eq(~rdmask
)
162 # reset write-operand mask
163 for idx
in range(cu
.n_dst
):
164 wrok
= cu
.get_out(idx
)
165 fname
= find_ok(wrok
.fields
)
166 yield getattr(wrok
, fname
).eq(0)
171 rd_rel_o
= yield cu
.rd
.rel
172 wr_rel_o
= yield cu
.wr
.rel
173 print ("before inputs, rd_rel, wr_rel: ",
174 bin(rd_rel_o
), bin(wr_rel_o
))
175 assert wr_rel_o
== 0, "wr.rel %s must be zero. "\
176 "previous instr not written all regs\n"\
178 (bin(wr_rel_o
), cu
.rwid
[1])
179 yield from set_cu_inputs(cu
, inp
)
181 rd_rel_o
= yield cu
.rd
.rel
182 wr_rel_o
= yield cu
.wr
.rel
183 wrmask
= yield cu
.wrmask
184 print ("after inputs, rd_rel, wr_rel, wrmask: ",
185 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
187 # call simulated operation
188 opname
= code
.split(' ')[0]
189 yield from sim
.call(opname
)
190 index
= sim
.pc
.CIA
.value
//4
193 # get all outputs (one by one, just "because")
194 res
= yield from get_cu_outputs(cu
, code
)
196 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
199 sim
.add_sync_process(process
)
200 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",