739f95fd2bdc0fdb2aa489320f08309f7c0bed69
[soc.git] / src / soc / fu / compunits / test / test_compunit.py
1 from nmigen import Module, Signal, ResetSignal
2 from nmigen.back.pysim import Simulator, Delay, Settle
3 from nmutil.formaltest import FHDLTestCase
4 from nmigen.cli import rtlil
5 import unittest
6 from soc.decoder.power_decoder import (create_pdecode)
7 from soc.decoder.power_decoder2 import (PowerDecode2)
8 from soc.decoder.power_enums import Function
9 from soc.decoder.isa.all import ISA
10
11 from soc.experiment.compalu_multi import find_ok # hack
12
13
14 def set_cu_input(cu, idx, data):
15 rdop = cu.get_in_name(idx)
16 yield cu.src_i[idx].eq(data)
17 while True:
18 rd_rel_o = yield cu.rd.rel[idx]
19 print ("rd_rel %d wait HI" % idx, rd_rel_o, rdop, hex(data))
20 if rd_rel_o:
21 break
22 yield
23 yield cu.rd.go[idx].eq(1)
24 while True:
25 yield
26 rd_rel_o = yield cu.rd.rel[idx]
27 if rd_rel_o:
28 break
29 print ("rd_rel %d wait HI" % idx, rd_rel_o)
30 yield
31 yield cu.rd.go[idx].eq(0)
32 yield cu.src_i[idx].eq(0)
33
34
35 def get_cu_output(cu, idx, code):
36 wrmask = yield cu.wrmask
37 wrop = cu.get_out_name(idx)
38 wrok = cu.get_out(idx)
39 fname = find_ok(wrok.fields)
40 wrok = yield getattr(wrok, fname)
41 print ("wr_rel mask", repr(code), idx, wrop, bin(wrmask), fname, wrok)
42 assert wrmask & (1<<idx), \
43 "get_cu_output '%s': mask bit %d not set\n" \
44 "write-operand '%s' Data.ok likely not set (%s)" \
45 % (code, idx, wrop, hex(wrok))
46 while True:
47 wr_relall_o = yield cu.wr.rel
48 wr_rel_o = yield cu.wr.rel[idx]
49 print ("wr_rel %d wait" % idx, hex(wr_relall_o), wr_rel_o)
50 if wr_rel_o:
51 break
52 yield
53 yield cu.wr.go[idx].eq(1)
54 yield Settle()
55 result = yield cu.dest[idx]
56 yield
57 yield cu.wr.go[idx].eq(0)
58 print ("result", repr(code), idx, wrop, wrok, hex(result))
59
60 return result
61
62
63 def set_cu_inputs(cu, inp):
64 for idx, data in inp.items():
65 yield from set_cu_input(cu, idx, data)
66
67
68 def set_operand(cu, dec2, sim):
69 yield from cu.oper_i.eq_from_execute1(dec2.e)
70 yield cu.issue_i.eq(1)
71 yield
72 yield cu.issue_i.eq(0)
73 yield
74
75
76 def get_cu_outputs(cu, code):
77 res = {}
78 wrmask = yield cu.wrmask
79 print ("get_cu_outputs", cu.n_dst, wrmask)
80 if not wrmask: # no point waiting (however really should doublecheck wr.rel)
81 return {}
82 # wait for at least one result
83 while True:
84 wr_rel_o = yield cu.wr.rel
85 if wr_rel_o:
86 break
87 yield
88 for i in range(cu.n_dst):
89 wr_rel_o = yield cu.wr.rel[i]
90 if wr_rel_o:
91 result = yield from get_cu_output(cu, i, code)
92 wrop = cu.get_out_name(i)
93 print ("output", i, wrop, hex(result))
94 res[wrop] = result
95 return res
96
97
98 def get_inp_indexed(cu, inp):
99 res = {}
100 for i in range(cu.n_src):
101 wrop = cu.get_in_name(i)
102 if wrop in inp:
103 res[i] = inp[wrop]
104 return res
105
106
107 class TestRunner(FHDLTestCase):
108 def __init__(self, test_data, fukls, iodef, funit):
109 super().__init__("run_all")
110 self.test_data = test_data
111 self.fukls = fukls
112 self.iodef = iodef
113 self.funit = funit
114
115 def run_all(self):
116 m = Module()
117 comb = m.d.comb
118 instruction = Signal(32)
119
120 pdecode = create_pdecode()
121
122 m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
123 if self.funit == Function.LDST:
124 from soc.experiment.l0_cache import TstL0CacheBuffer
125 m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64,
126 addrwid=4)
127 pi = l0.l0.dports[0].pi
128 m.submodules.cu = cu = self.fukls(pi, awid=3)
129 m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
130 m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
131 else:
132 m.submodules.cu = cu = self.fukls()
133
134 comb += pdecode2.dec.raw_opcode_in.eq(instruction)
135 sim = Simulator(m)
136
137 sim.add_clock(1e-6)
138
139 def process():
140 yield cu.issue_i.eq(0)
141 yield
142
143 for test in self.test_data:
144 print(test.name)
145 program = test.program
146 self.subTest(test.name)
147 print ("test", test.name, test.mem)
148 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
149 test.msr)
150 gen = program.generate_instructions()
151 instructions = list(zip(gen, program.assembly.splitlines()))
152
153 # initialise memory
154 if self.funit == Function.LDST:
155 mem = l0.mem.mem
156 print ("before, init mem", mem.depth, mem.width, mem)
157 for i in range(mem.depth):
158 data = sim.mem.ld(i*8, 8)
159 print ("init ", i, hex(data))
160 yield mem._array[i].eq(data)
161 yield Settle()
162 for k, v in sim.mem.mem.items():
163 print (" %6x %016x" % (k, v))
164 print ("before, nmigen mem dump")
165 for i in range(mem.depth):
166 actual_mem = yield mem._array[i]
167 print (" %6i %016x" % (i, actual_mem))
168
169
170 index = sim.pc.CIA.value//4
171 while index < len(instructions):
172 ins, code = instructions[index]
173
174 print("0x{:X}".format(ins & 0xffffffff))
175 print(code)
176
177 # ask the decoder to decode this binary data (endian'd)
178 yield pdecode2.dec.bigendian.eq(0) # little / big?
179 yield instruction.eq(ins) # raw binary instr.
180 yield Settle()
181 fn_unit = yield pdecode2.e.fn_unit
182 fuval = self.funit.value
183 self.assertEqual(fn_unit & fuval, fuval)
184
185 # set operand and get inputs
186 yield from set_operand(cu, pdecode2, sim)
187 iname = yield from self.iodef.get_cu_inputs(pdecode2, sim)
188 inp = get_inp_indexed(cu, iname)
189
190 # reset read-operand mask
191 rdmask = pdecode2.rdflags(cu)
192 #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
193 #print ("decoder rdmask", rdmask)
194 yield cu.rdmaskn.eq(~rdmask)
195
196 # reset write-operand mask
197 for idx in range(cu.n_dst):
198 wrok = cu.get_out(idx)
199 fname = find_ok(wrok.fields)
200 yield getattr(wrok, fname).eq(0)
201
202 yield Settle()
203
204 # set inputs into CU
205 rd_rel_o = yield cu.rd.rel
206 wr_rel_o = yield cu.wr.rel
207 print ("before inputs, rd_rel, wr_rel: ",
208 bin(rd_rel_o), bin(wr_rel_o))
209 assert wr_rel_o == 0, "wr.rel %s must be zero. "\
210 "previous instr not written all regs\n"\
211 "respec %s" % \
212 (bin(wr_rel_o), cu.rwid[1])
213 yield from set_cu_inputs(cu, inp)
214 rd_rel_o = yield cu.rd.rel
215 wr_rel_o = yield cu.wr.rel
216 wrmask = yield cu.wrmask
217 print ("after inputs, rd_rel, wr_rel, wrmask: ",
218 bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
219
220 # call simulated operation
221 opname = code.split(' ')[0]
222 yield from sim.call(opname)
223 index = sim.pc.CIA.value//4
224
225 yield Settle()
226 # get all outputs (one by one, just "because")
227 res = yield from get_cu_outputs(cu, code)
228 wrmask = yield cu.wrmask
229 rd_rel_o = yield cu.rd.rel
230 wr_rel_o = yield cu.wr.rel
231 print ("after got outputs, rd_rel, wr_rel, wrmask: ",
232 bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
233
234 # wait for busy to go low
235 while True:
236 busy_o = yield cu.busy_o
237 print ("busy", busy_o)
238 if not busy_o:
239 break
240 yield
241
242 yield from self.iodef.check_cu_outputs(res, pdecode2,
243 sim, code)
244
245 # sigh. hard-coded. test memory
246 if self.funit == Function.LDST:
247 mem = l0.mem.mem
248 print ("sim mem dump")
249 for k, v in sim.mem.mem.items():
250 print (" %6x %016x" % (k, v))
251 print ("nmigen mem dump")
252 for i in range(mem.depth):
253 actual_mem = yield mem._array[i]
254 print (" %6i %016x" % (i, actual_mem))
255
256 for i in range(mem.depth):
257 expected_mem = sim.mem.ld(i*8, 8)
258 actual_mem = yield mem._array[i]
259 self.assertEqual(expected_mem, actual_mem,
260 "%s %d %x %x" % (code, i,
261 expected_mem, actual_mem))
262
263
264 sim.add_sync_process(process)
265
266 name = self.funit.name.lower()
267 with sim.write_vcd("%s_simulator.vcd" % name,
268 "%s_simulator.gtkw" % name,
269 traces=[]):
270 sim.run()
271
272