7a73cb83f5f61d29d612b18a0b522e68ff2738ef
1 from nmigen
import Module
, Signal
, ResetSignal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.power_decoder
import (create_pdecode
)
7 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
8 from soc
.decoder
.power_enums
import Function
9 from soc
.decoder
.isa
.all
import ISA
11 from soc
.experiment
.compalu_multi
import find_ok
# hack
12 from soc
.config
.test
.test_loadstore
import TestMemPspec
15 def set_cu_input(cu
, idx
, data
):
16 rdop
= cu
.get_in_name(idx
)
17 yield cu
.src_i
[idx
].eq(data
)
19 rd_rel_o
= yield cu
.rd
.rel
[idx
]
20 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
24 yield cu
.rd
.go
[idx
].eq(1)
27 rd_rel_o
= yield cu
.rd
.rel
[idx
]
30 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
32 yield cu
.rd
.go
[idx
].eq(0)
33 yield cu
.src_i
[idx
].eq(0)
36 def get_cu_output(cu
, idx
, code
):
37 wrmask
= yield cu
.wrmask
38 wrop
= cu
.get_out_name(idx
)
39 wrok
= cu
.get_out(idx
)
40 fname
= find_ok(wrok
.fields
)
41 wrok
= yield getattr(wrok
, fname
)
42 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
43 assert wrmask
& (1<<idx
), \
44 "get_cu_output '%s': mask bit %d not set\n" \
45 "write-operand '%s' Data.ok likely not set (%s)" \
46 % (code
, idx
, wrop
, hex(wrok
))
48 wr_relall_o
= yield cu
.wr
.rel
49 wr_rel_o
= yield cu
.wr
.rel
[idx
]
50 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
54 yield cu
.wr
.go
[idx
].eq(1)
56 result
= yield cu
.dest
[idx
]
58 yield cu
.wr
.go
[idx
].eq(0)
59 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
64 def set_cu_inputs(cu
, inp
):
65 print ("set_cu_inputs", inp
)
66 for idx
, data
in inp
.items():
67 yield from set_cu_input(cu
, idx
, data
)
70 def set_operand(cu
, dec2
, sim
):
71 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
72 yield cu
.issue_i
.eq(1)
74 yield cu
.issue_i
.eq(0)
78 def get_cu_outputs(cu
, code
):
80 wrmask
= yield cu
.wrmask
81 print ("get_cu_outputs", cu
.n_dst
, wrmask
)
82 if not wrmask
: # no point waiting (however really should doublecheck wr.rel)
84 # wait for at least one result
86 wr_rel_o
= yield cu
.wr
.rel
90 for i
in range(cu
.n_dst
):
91 wr_rel_o
= yield cu
.wr
.rel
[i
]
93 result
= yield from get_cu_output(cu
, i
, code
)
94 wrop
= cu
.get_out_name(i
)
95 print ("output", i
, wrop
, hex(result
))
100 def get_inp_indexed(cu
, inp
):
102 for i
in range(cu
.n_src
):
103 wrop
= cu
.get_in_name(i
)
108 def get_l0_mem(l0
): # BLECH!
109 if hasattr(l0
.pimem
, 'lsui'):
110 return l0
.pimem
.lsui
.mem
111 return l0
.pimem
.mem
.mem
113 def setup_test_memory(l0
, sim
):
115 print ("before, init mem", mem
.depth
, mem
.width
, mem
)
116 for i
in range(mem
.depth
):
117 data
= sim
.mem
.ld(i
*8, 8, False)
118 print ("init ", i
, hex(data
))
119 yield mem
._array
[i
].eq(data
)
121 for k
, v
in sim
.mem
.mem
.items():
122 print (" %6x %016x" % (k
, v
))
123 print ("before, nmigen mem dump")
124 for i
in range(mem
.depth
):
125 actual_mem
= yield mem
._array
[i
]
126 print (" %6i %016x" % (i
, actual_mem
))
129 def dump_sim_memory(dut
, l0
, sim
, code
):
131 print ("sim mem dump")
132 for k
, v
in sim
.mem
.mem
.items():
133 print (" %6x %016x" % (k
, v
))
134 print ("nmigen mem dump")
135 for i
in range(mem
.depth
):
136 actual_mem
= yield mem
._array
[i
]
137 print (" %6i %016x" % (i
, actual_mem
))
140 def check_sim_memory(dut
, l0
, sim
, code
):
143 for i
in range(mem
.depth
):
144 expected_mem
= sim
.mem
.ld(i
*8, 8, False)
145 actual_mem
= yield mem
._array
[i
]
146 dut
.assertEqual(expected_mem
, actual_mem
,
147 "%s %d %x %x" % (code
, i
,
148 expected_mem
, actual_mem
))
150 class TestRunner(FHDLTestCase
):
151 def __init__(self
, test_data
, fukls
, iodef
, funit
, bigendian
):
152 super().__init
__("run_all")
153 self
.test_data
= test_data
157 self
.bigendian
= bigendian
162 instruction
= Signal(32)
164 pdecode
= create_pdecode()
165 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
167 # copy of the decoder for simulator
168 simdec
= create_pdecode()
169 simdec2
= PowerDecode2(simdec
)
170 m
.submodules
.simdec2
= simdec2
# pain in the neck
172 if self
.funit
== Function
.LDST
:
173 from soc
.experiment
.l0_cache
import TstL0CacheBuffer
174 pspec
= TestMemPspec(ldst_ifacetype
='test_bare_wb',
178 m
.submodules
.l0
= l0
= TstL0CacheBuffer(pspec
, n_units
=1)
180 m
.submodules
.cu
= cu
= self
.fukls(pi
, idx
=0, awid
=3)
181 m
.d
.comb
+= cu
.ad
.go
.eq(cu
.ad
.rel
) # link addr-go direct to rel
182 m
.d
.comb
+= cu
.st
.go
.eq(cu
.st
.rel
) # link store-go direct to rel
184 m
.submodules
.cu
= cu
= self
.fukls(0)
186 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
192 yield cu
.issue_i
.eq(0)
195 for test
in self
.test_data
:
197 program
= test
.program
198 self
.subTest(test
.name
)
199 print ("test", test
.name
, test
.mem
)
200 gen
= list(program
.generate_instructions())
201 insncode
= program
.assembly
.splitlines()
202 instructions
= list(zip(gen
, insncode
))
203 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
205 initial_insns
=gen
, respect_pc
=False,
206 disassembly
=insncode
,
207 bigendian
=self
.bigendian
)
210 if self
.funit
== Function
.LDST
:
211 yield from setup_test_memory(l0
, sim
)
213 index
= sim
.pc
.CIA
.value
//4
216 yield from sim
.setup_one()
217 except KeyError: # indicates instruction not in imem: stop
220 ins
, code
= instructions
[index
]
223 # ask the decoder to decode this binary data (endian'd)
224 yield pdecode2
.dec
.bigendian
.eq(self
.bigendian
) # le / be?
225 yield instruction
.eq(ins
) # raw binary instr.
227 fn_unit
= yield pdecode2
.e
.do
.fn_unit
228 fuval
= self
.funit
.value
229 self
.assertEqual(fn_unit
& fuval
, fuval
)
231 # set operand and get inputs
232 yield from set_operand(cu
, pdecode2
, sim
)
234 iname
= yield from self
.iodef
.get_cu_inputs(pdecode2
, sim
)
235 inp
= get_inp_indexed(cu
, iname
)
237 # reset read-operand mask
238 rdmask
= pdecode2
.rdflags(cu
)
239 #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
240 #print ("decoder rdmask", rdmask)
241 yield cu
.rdmaskn
.eq(~rdmask
)
243 # reset write-operand mask
244 for idx
in range(cu
.n_dst
):
245 wrok
= cu
.get_out(idx
)
246 fname
= find_ok(wrok
.fields
)
247 yield getattr(wrok
, fname
).eq(0)
252 rd_rel_o
= yield cu
.rd
.rel
253 wr_rel_o
= yield cu
.wr
.rel
254 print ("before inputs, rd_rel, wr_rel: ",
255 bin(rd_rel_o
), bin(wr_rel_o
))
256 assert wr_rel_o
== 0, "wr.rel %s must be zero. "\
257 "previous instr not written all regs\n"\
259 (bin(wr_rel_o
), cu
.rwid
[1])
260 yield from set_cu_inputs(cu
, inp
)
261 rd_rel_o
= yield cu
.rd
.rel
262 wr_rel_o
= yield cu
.wr
.rel
263 wrmask
= yield cu
.wrmask
264 print ("after inputs, rd_rel, wr_rel, wrmask: ",
265 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
267 # call simulated operation
268 yield from sim
.execute_one()
270 index
= sim
.pc
.CIA
.value
//4
272 # get all outputs (one by one, just "because")
273 res
= yield from get_cu_outputs(cu
, code
)
274 wrmask
= yield cu
.wrmask
275 rd_rel_o
= yield cu
.rd
.rel
276 wr_rel_o
= yield cu
.wr
.rel
277 print ("after got outputs, rd_rel, wr_rel, wrmask: ",
278 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
280 # wait for busy to go low
282 busy_o
= yield cu
.busy_o
283 print ("busy", busy_o
)
288 if self
.funit
== Function
.LDST
:
289 yield from dump_sim_memory(self
, l0
, sim
, code
)
292 # sigh. hard-coded. test memory
293 if self
.funit
== Function
.LDST
:
294 yield from check_sim_memory(self
, l0
, sim
, code
)
295 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
299 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
304 sim
.add_sync_process(process
)
306 name
= self
.funit
.name
.lower()
307 with sim
.write_vcd("%s_simulator.vcd" % name
,
308 "%s_simulator.gtkw" % name
,