1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmigen
.test
.utils
import FHDLTestCase
4 from nmigen
.cli
import rtlil
6 from soc
.decoder
.isa
.caller
import ISACaller
, special_sprs
7 from soc
.decoder
.power_decoder
import (create_pdecode
)
8 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
9 from soc
.decoder
.power_enums
import (XER_bits
, Function
, InternalOp
)
10 from soc
.decoder
.selectable_int
import SelectableInt
11 from soc
.simulator
.program
import Program
12 from soc
.decoder
.isa
.all
import ISA
14 from soc
.fu
.alu
.test
.test_pipe_caller
import TestCase
, ALUTestCase
, test_data
15 from soc
.experiment
.compalu_multi
import find_ok
# hack
18 def set_cu_input(cu
, idx
, data
):
19 rdop
= cu
.get_in_name(idx
)
20 yield cu
.src_i
[idx
].eq(data
)
22 rd_rel_o
= yield cu
.rd
.rel
[idx
]
23 print ("rd_rel %d wait HI" % idx
, rd_rel_o
, rdop
, hex(data
))
27 yield cu
.rd
.go
[idx
].eq(1)
30 rd_rel_o
= yield cu
.rd
.rel
[idx
]
33 print ("rd_rel %d wait HI" % idx
, rd_rel_o
)
35 yield cu
.rd
.go
[idx
].eq(0)
38 def get_cu_output(cu
, idx
, code
):
39 wrmask
= yield cu
.wrmask
40 wrop
= cu
.get_out_name(idx
)
41 wrok
= cu
.get_out(idx
)
42 fname
= find_ok(wrok
.fields
)
43 wrok
= yield getattr(wrok
, fname
)
44 print ("wr_rel mask", repr(code
), idx
, wrop
, bin(wrmask
), fname
, wrok
)
45 assert wrmask
& (1<<idx
), \
46 "get_cu_output '%s': mask bit %d not set\n" \
47 "write-operand '%s' Data.ok likely not set (%s)" \
48 % (code
, idx
, wrop
, hex(wrok
))
50 wr_relall_o
= yield cu
.wr
.rel
51 wr_rel_o
= yield cu
.wr
.rel
[idx
]
52 print ("wr_rel %d wait" % idx
, hex(wr_relall_o
), wr_rel_o
)
56 yield cu
.wr
.go
[idx
].eq(1)
58 result
= yield cu
.dest
[idx
]
60 yield cu
.wr
.go
[idx
].eq(0)
61 print ("result", repr(code
), idx
, wrop
, wrok
, hex(result
))
65 def set_cu_inputs(cu
, inp
):
66 for idx
, data
in inp
.items():
67 yield from set_cu_input(cu
, idx
, data
)
70 def set_operand(cu
, dec2
, sim
):
71 yield from cu
.oper_i
.eq_from_execute1(dec2
.e
)
72 yield cu
.issue_i
.eq(1)
74 yield cu
.issue_i
.eq(0)
78 def get_cu_outputs(cu
, code
):
80 for i
in range(cu
.n_dst
):
81 wr_rel_o
= yield cu
.wr
.rel
[i
]
83 result
= yield from get_cu_output(cu
, i
, code
)
84 wrop
= cu
.get_out_name(i
)
85 print ("output", i
, wrop
, hex(result
))
90 def get_inp_indexed(cu
, inp
):
92 for i
in range(cu
.n_src
):
93 wrop
= cu
.get_in_name(i
)
98 def get_cu_rd_mask(n_src
, inp
):
100 for i
in range(n_src
):
106 class TestRunner(FHDLTestCase
):
107 def __init__(self
, test_data
, fukls
, iodef
, funit
):
108 super().__init
__("run_all")
109 self
.test_data
= test_data
117 instruction
= Signal(32)
119 pdecode
= create_pdecode()
121 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
122 m
.submodules
.cu
= cu
= self
.fukls()
124 comb
+= pdecode2
.dec
.raw_opcode_in
.eq(instruction
)
130 yield cu
.issue_i
.eq(0)
133 for test
in self
.test_data
:
135 program
= test
.program
136 self
.subTest(test
.name
)
137 sim
= ISA(pdecode2
, test
.regs
, test
.sprs
, 0)
138 gen
= program
.generate_instructions()
139 instructions
= list(zip(gen
, program
.assembly
.splitlines()))
141 index
= sim
.pc
.CIA
.value
//4
142 while index
< len(instructions
):
143 ins
, code
= instructions
[index
]
145 print("0x{:X}".format(ins
& 0xffffffff))
148 # ask the decoder to decode this binary data (endian'd)
149 yield pdecode2
.dec
.bigendian
.eq(0) # little / big?
150 yield instruction
.eq(ins
) # raw binary instr.
152 fn_unit
= yield pdecode2
.e
.fn_unit
153 self
.assertEqual(fn_unit
, self
.funit
.value
)
155 # set operand and get inputs
156 yield from set_operand(cu
, pdecode2
, sim
)
157 iname
= yield from self
.iodef
.get_cu_inputs(pdecode2
, sim
)
158 inp
= get_inp_indexed(cu
, iname
)
160 # reset read-operand mask
161 rdmask
= get_cu_rd_mask(cu
.n_src
, inp
)
162 yield cu
.rdmaskn
.eq(~rdmask
)
164 # reset write-operand mask
165 for idx
in range(cu
.n_dst
):
166 wrok
= cu
.get_out(idx
)
167 fname
= find_ok(wrok
.fields
)
168 yield getattr(wrok
, fname
).eq(0)
171 rd_rel_o
= yield cu
.rd
.rel
172 wr_rel_o
= yield cu
.wr
.rel
173 print ("before inputs, rd_rel, wr_rel: ",
174 bin(rd_rel_o
), bin(wr_rel_o
))
175 yield from set_cu_inputs(cu
, inp
)
177 rd_rel_o
= yield cu
.rd
.rel
178 wr_rel_o
= yield cu
.wr
.rel
179 wrmask
= yield cu
.wrmask
180 print ("after inputs, rd_rel, wr_rel, wrmask: ",
181 bin(rd_rel_o
), bin(wr_rel_o
), bin(wrmask
))
183 # call simulated operation
184 opname
= code
.split(' ')[0]
185 yield from sim
.call(opname
)
186 index
= sim
.pc
.CIA
.value
//4
188 # get all outputs (one by one, just "because")
189 res
= yield from get_cu_outputs(cu
, code
)
191 yield from self
.iodef
.check_cu_outputs(res
, pdecode2
,
194 sim
.add_sync_process(process
)
195 with sim
.write_vcd("simulator.vcd", "simulator.gtkw",