src/soc/fu/compunits/test/test_compunit.py

   1 from nmigen import Module, Signal, ResetSignal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmutil.formaltest import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.power_decoder import (create_pdecode)
   7 from soc.decoder.power_decoder2 import (PowerDecode2)
   8 from soc.decoder.power_enums import Function
   9 from soc.decoder.isa.all import ISA
  10
  11 from soc.experiment.compalu_multi import find_ok # hack
  12
  13
  14 def set_cu_input(cu, idx, data):
  15     rdop = cu.get_in_name(idx)
  16     yield cu.src_i[idx].eq(data)
  17     while True:
  18         rd_rel_o = yield cu.rd.rel[idx]
  19         print ("rd_rel %d wait HI" % idx, rd_rel_o, rdop, hex(data))
  20         if rd_rel_o:
  21             break
  22         yield
  23     yield cu.rd.go[idx].eq(1)
  24     while True:
  25         yield
  26         rd_rel_o = yield cu.rd.rel[idx]
  27         if rd_rel_o:
  28             break
  29         print ("rd_rel %d wait HI" % idx, rd_rel_o)
  30         yield
  31     yield cu.rd.go[idx].eq(0)
  32     yield cu.src_i[idx].eq(0)
  33
  34
  35 def get_cu_output(cu, idx, code):
  36     wrmask = yield cu.wrmask
  37     wrop = cu.get_out_name(idx)
  38     wrok = cu.get_out(idx)
  39     fname = find_ok(wrok.fields)
  40     wrok = yield getattr(wrok, fname)
  41     print ("wr_rel mask", repr(code), idx, wrop, bin(wrmask), fname, wrok)
  42     assert wrmask & (1<<idx), \
  43             "get_cu_output '%s': mask bit %d not set\n" \
  44             "write-operand '%s' Data.ok likely not set (%s)" \
  45             % (code, idx, wrop, hex(wrok))
  46     while True:
  47         wr_relall_o = yield cu.wr.rel
  48         wr_rel_o = yield cu.wr.rel[idx]
  49         print ("wr_rel %d wait" % idx, hex(wr_relall_o), wr_rel_o)
  50         if wr_rel_o:
  51             break
  52         yield
  53     yield cu.wr.go[idx].eq(1)
  54     yield Settle()
  55     result = yield cu.dest[idx]
  56     yield
  57     yield cu.wr.go[idx].eq(0)
  58     print ("result", repr(code), idx, wrop, wrok, hex(result))
  59     return result
  60
  61
  62 def set_cu_inputs(cu, inp):
  63     for idx, data in inp.items():
  64         yield from set_cu_input(cu, idx, data)
  65
  66
  67 def set_operand(cu, dec2, sim):
  68     yield from cu.oper_i.eq_from_execute1(dec2.e)
  69     yield cu.issue_i.eq(1)
  70     yield
  71     yield cu.issue_i.eq(0)
  72     yield
  73
  74
  75 def get_cu_outputs(cu, code):
  76     res = {}
  77     wrmask = yield cu.wrmask
  78     print ("get_cu_outputs", cu.n_dst, wrmask)
  79     if not wrmask: # no point waiting (however really should doublecheck wr.rel)
  80         return {}
  81     # wait for at least one result
  82     while True:
  83         wr_rel_o = yield cu.wr.rel
  84         if wr_rel_o:
  85             break
  86         yield
  87     for i in range(cu.n_dst):
  88         wr_rel_o = yield cu.wr.rel[i]
  89         if wr_rel_o:
  90             result = yield from get_cu_output(cu, i, code)
  91             wrop = cu.get_out_name(i)
  92             print ("output", i, wrop, hex(result))
  93             res[wrop] = result
  94     return res
  95
  96
  97 def get_inp_indexed(cu, inp):
  98     res = {}
  99     for i in range(cu.n_src):
 100         wrop = cu.get_in_name(i)
 101         if wrop in inp:
 102             res[i] = inp[wrop]
 103     return res
 104
 105
 106 class TestRunner(FHDLTestCase):
 107     def __init__(self, test_data, fukls, iodef, funit):
 108         super().__init__("run_all")
 109         self.test_data = test_data
 110         self.fukls = fukls
 111         self.iodef = iodef
 112         self.funit = funit
 113
 114     def run_all(self):
 115         m = Module()
 116         comb = m.d.comb
 117         instruction = Signal(32)
 118
 119         pdecode = create_pdecode()
 120
 121         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 122         if self.funit == Function.LDST:
 123             from soc.experiment.l0_cache import TstL0CacheBuffer
 124             m.submodules.l0 = l0 = TstL0CacheBuffer(n_units=1, regwid=64)
 125             pi = l0.l0.dports[0].pi
 126             m.submodules.cu = cu = self.fukls(pi, awid=4)
 127             m.d.comb += cu.ad.go.eq(cu.ad.rel) # link addr-go direct to rel
 128             m.d.comb += cu.st.go.eq(cu.st.rel) # link store-go direct to rel
 129         else:
 130             m.submodules.cu = cu = self.fukls()
 131
 132         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 133         sim = Simulator(m)
 134
 135         sim.add_clock(1e-6)
 136
 137         def process():
 138             yield cu.issue_i.eq(0)
 139             yield
 140
 141             for test in self.test_data:
 142                 print(test.name)
 143                 program = test.program
 144                 self.subTest(test.name)
 145                 print ("test", test.name, test.mem)
 146                 sim = ISA(pdecode2, test.regs, test.sprs, test.cr, test.mem,
 147                           test.msr)
 148                 gen = program.generate_instructions()
 149                 instructions = list(zip(gen, program.assembly.splitlines()))
 150
 151                 # initialise memory
 152                 if self.funit == Function.LDST:
 153                     mem = l0.mem.mem
 154                     memlist = []
 155                     for i in range(mem.depth//2):
 156                         data = sim.mem.ld(i*16, 8)
 157                         data1 = sim.mem.ld(i*16+8, 8)
 158                         yield mem._array[i].eq(data | (data1<<32))
 159                     print (mem, mem.depth, mem.width)
 160                     print ("mem init", list(map(hex,memlist)))
 161
 162                 index = sim.pc.CIA.value//4
 163                 while index < len(instructions):
 164                     ins, code = instructions[index]
 165
 166                     print("0x{:X}".format(ins & 0xffffffff))
 167                     print(code)
 168
 169                     # ask the decoder to decode this binary data (endian'd)
 170                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 171                     yield instruction.eq(ins)          # raw binary instr.
 172                     yield Settle()
 173                     fn_unit = yield pdecode2.e.fn_unit
 174                     fuval = self.funit.value
 175                     self.assertEqual(fn_unit & fuval, fuval)
 176
 177                     # set operand and get inputs
 178                     yield from set_operand(cu, pdecode2, sim)
 179                     iname = yield from self.iodef.get_cu_inputs(pdecode2, sim)
 180                     inp = get_inp_indexed(cu, iname)
 181
 182                     # reset read-operand mask
 183                     rdmask = pdecode2.rdflags(cu)
 184                     #print ("hardcoded rdmask", cu.rdflags(pdecode2.e))
 185                     #print ("decoder rdmask", rdmask)
 186                     yield cu.rdmaskn.eq(~rdmask)
 187
 188                     # reset write-operand mask
 189                     for idx in range(cu.n_dst):
 190                         wrok = cu.get_out(idx)
 191                         fname = find_ok(wrok.fields)
 192                         yield getattr(wrok, fname).eq(0)
 193
 194                     yield Settle()
 195
 196                     # set inputs into CU
 197                     rd_rel_o = yield cu.rd.rel
 198                     wr_rel_o = yield cu.wr.rel
 199                     print ("before inputs, rd_rel, wr_rel: ",
 200                             bin(rd_rel_o), bin(wr_rel_o))
 201                     assert wr_rel_o == 0, "wr.rel %s must be zero. "\
 202                                 "previous instr not written all regs\n"\
 203                                 "respec %s" % \
 204                                 (bin(wr_rel_o), cu.rwid[1])
 205                     yield from set_cu_inputs(cu, inp)
 206                     yield
 207                     rd_rel_o = yield cu.rd.rel
 208                     wr_rel_o = yield cu.wr.rel
 209                     wrmask = yield cu.wrmask
 210                     print ("after inputs, rd_rel, wr_rel, wrmask: ",
 211                             bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 212
 213                     # call simulated operation
 214                     opname = code.split(' ')[0]
 215                     yield from sim.call(opname)
 216                     index = sim.pc.CIA.value//4
 217
 218                     yield Settle()
 219                     # get all outputs (one by one, just "because")
 220                     res = yield from get_cu_outputs(cu, code)
 221
 222                     yield from self.iodef.check_cu_outputs(res, pdecode2,
 223                                                             sim, code)
 224
 225                     # sigh.  hard-coded.  test memory
 226                     if self.funit == Function.LDST:
 227                         print ("mem dump", sim.mem.mem)
 228
 229         sim.add_sync_process(process)
 230
 231         name = self.funit.name.lower()
 232         with sim.write_vcd("%s_simulator.vcd" % name,
 233                            "%s_simulator.gtkw" % name,
 234                             traces=[]):
 235             sim.run()
 236
 237