src/soc/fu/compunits/test/test_compunit.py

   1 from nmigen import Module, Signal
   2 from nmigen.back.pysim import Simulator, Delay, Settle
   3 from nmigen.test.utils import FHDLTestCase
   4 from nmigen.cli import rtlil
   5 import unittest
   6 from soc.decoder.isa.caller import ISACaller, special_sprs
   7 from soc.decoder.power_decoder import (create_pdecode)
   8 from soc.decoder.power_decoder2 import (PowerDecode2)
   9 from soc.decoder.power_enums import (XER_bits, Function, InternalOp)
  10 from soc.decoder.selectable_int import SelectableInt
  11 from soc.simulator.program import Program
  12 from soc.decoder.isa.all import ISA
  13
  14 from soc.fu.alu.test.test_pipe_caller import TestCase, ALUTestCase, test_data
  15 from soc.experiment.compalu_multi import find_ok # hack
  16 import random
  17
  18 def set_cu_input(cu, idx, data):
  19     rdop = cu.get_in_name(idx)
  20     yield cu.src_i[idx].eq(data)
  21     while True:
  22         rd_rel_o = yield cu.rd.rel[idx]
  23         print ("rd_rel %d wait HI" % idx, rd_rel_o, rdop, hex(data))
  24         if rd_rel_o:
  25             break
  26         yield
  27     yield cu.rd.go[idx].eq(1)
  28     while True:
  29         yield
  30         rd_rel_o = yield cu.rd.rel[idx]
  31         if rd_rel_o:
  32             break
  33         print ("rd_rel %d wait HI" % idx, rd_rel_o)
  34         yield
  35     yield cu.rd.go[idx].eq(0)
  36
  37
  38 def get_cu_output(cu, idx, code):
  39     wrmask = yield cu.wrmask
  40     wrop = cu.get_out_name(idx)
  41     wrok = cu.get_out(idx)
  42     fname = find_ok(wrok.fields)
  43     wrok = yield getattr(wrok, fname)
  44     print ("wr_rel mask", repr(code), idx, wrop, bin(wrmask), fname, wrok)
  45     assert wrmask & (1<<idx), \
  46             "get_cu_output '%s': mask bit %d not set\n" \
  47             "write-operand '%s' Data.ok likely not set (%s)" \
  48             % (code, idx, wrop, hex(wrok))
  49     while True:
  50         wr_relall_o = yield cu.wr.rel
  51         wr_rel_o = yield cu.wr.rel[idx]
  52         print ("wr_rel %d wait" % idx, hex(wr_relall_o), wr_rel_o)
  53         if wr_rel_o:
  54             break
  55         yield
  56     yield cu.wr.go[idx].eq(1)
  57     yield Settle()
  58     result = yield cu.dest[idx]
  59     yield
  60     yield cu.wr.go[idx].eq(0)
  61     print ("result", repr(code), idx, wrop, wrok, hex(result))
  62     return result
  63
  64
  65 def set_cu_inputs(cu, inp):
  66     for idx, data in inp.items():
  67         yield from set_cu_input(cu, idx, data)
  68
  69
  70 def set_operand(cu, dec2, sim):
  71     yield from cu.oper_i.eq_from_execute1(dec2.e)
  72     yield cu.issue_i.eq(1)
  73     yield
  74     yield cu.issue_i.eq(0)
  75     yield
  76
  77
  78 def get_cu_outputs(cu, code):
  79     res = {}
  80     for i in range(cu.n_dst):
  81         wr_rel_o = yield cu.wr.rel[i]
  82         if wr_rel_o:
  83             result = yield from get_cu_output(cu, i, code)
  84             wrop = cu.get_out_name(i)
  85             print ("output", i, wrop, hex(result))
  86             res[wrop] = result
  87     return res
  88
  89
  90 def get_cu_rd_mask(n_src, inp):
  91     mask = 0 #((1<<n_src)-1)
  92     for i in inp.keys():
  93         mask |= 1<<i
  94     return mask
  95
  96
  97 class TestRunner(FHDLTestCase):
  98     def __init__(self, test_data, fukls, iodef):
  99         super().__init__("run_all")
 100         self.test_data = test_data
 101         self.fukls = fukls
 102         self.iodef = iodef
 103
 104     def run_all(self):
 105         m = Module()
 106         comb = m.d.comb
 107         instruction = Signal(32)
 108
 109         pdecode = create_pdecode()
 110
 111         m.submodules.pdecode2 = pdecode2 = PowerDecode2(pdecode)
 112         m.submodules.cu = cu = self.fukls()
 113
 114         comb += pdecode2.dec.raw_opcode_in.eq(instruction)
 115         sim = Simulator(m)
 116
 117         sim.add_clock(1e-6)
 118
 119         def process():
 120             yield cu.issue_i.eq(0)
 121             yield
 122
 123             for test in self.test_data:
 124                 print(test.name)
 125                 program = test.program
 126                 self.subTest(test.name)
 127                 sim = ISA(pdecode2, test.regs, test.sprs, 0)
 128                 gen = program.generate_instructions()
 129                 instructions = list(zip(gen, program.assembly.splitlines()))
 130
 131                 index = sim.pc.CIA.value//4
 132                 while index < len(instructions):
 133                     ins, code = instructions[index]
 134
 135                     print("0x{:X}".format(ins & 0xffffffff))
 136                     print(code)
 137
 138                     # ask the decoder to decode this binary data (endian'd)
 139                     yield pdecode2.dec.bigendian.eq(0)  # little / big?
 140                     yield instruction.eq(ins)          # raw binary instr.
 141                     yield Settle()
 142                     fn_unit = yield pdecode2.e.fn_unit
 143                     self.assertEqual(fn_unit, Function.ALU.value)
 144
 145                     # set operand and get inputs
 146                     yield from set_operand(cu, pdecode2, sim)
 147                     inp = yield from self.iodef.get_cu_inputs(pdecode2, sim)
 148
 149                     # reset read-operand mask
 150                     rdmask = get_cu_rd_mask(cu.n_src, inp)
 151                     yield cu.rdmaskn.eq(~rdmask)
 152
 153                     # reset write-operand mask
 154                     for idx in range(cu.n_dst):
 155                         wrok = cu.get_out(idx)
 156                         fname = find_ok(wrok.fields)
 157                         yield getattr(wrok, fname).eq(0)
 158
 159                     # set inputs into CU
 160                     rd_rel_o = yield cu.rd.rel
 161                     wr_rel_o = yield cu.wr.rel
 162                     print ("before inputs, rd_rel, wr_rel: ",
 163                             bin(rd_rel_o), bin(wr_rel_o))
 164                     yield from set_cu_inputs(cu, inp)
 165                     yield
 166                     rd_rel_o = yield cu.rd.rel
 167                     wr_rel_o = yield cu.wr.rel
 168                     wrmask = yield cu.wrmask
 169                     print ("after inputs, rd_rel, wr_rel, wrmask: ",
 170                             bin(rd_rel_o), bin(wr_rel_o), bin(wrmask))
 171
 172                     # call simulated operation
 173                     opname = code.split(' ')[0]
 174                     yield from sim.call(opname)
 175                     index = sim.pc.CIA.value//4
 176
 177                     # get all outputs (one by one, just "because")
 178                     res = yield from get_cu_outputs(cu, code)
 179
 180                     yield from self.iodef.check_cu_outputs(res, pdecode2,
 181                                                             sim, code)
 182
 183         sim.add_sync_process(process)
 184         with sim.write_vcd("simulator.vcd", "simulator.gtkw",
 185                             traces=[]):
 186             sim.run()
 187
 188