cf8572e9be6600f58561bc8568e3a1dac89d493b
2 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
4 # XXX bad practice: use of global variables
5 from soc
.fu
.cr
.test
.test_pipe_caller
import CRTestCase
6 from soc
.fu
.cr
.test
.test_pipe_caller
import test_data
8 from soc
.fu
.compunits
.compunits
import CRFunctionUnit
9 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
12 class CRTestRunner(TestRunner
):
13 def __init__(self
, test_data
):
14 super().__init
__(test_data
, CRFunctionUnit
, self
,
17 def get_cu_inputs(self
, dec2
, sim
):
18 """naming (res) must conform to CRFunctionUnit input regspec
21 full_reg
= yield dec2
.e
.read_cr_whole
24 print(sim
.cr
.get_range().value
)
26 res
['full_cr'] = sim
.cr
.get_range().value
29 cr1_en
= yield dec2
.e
.read_cr1
.ok
31 cr1_sel
= yield dec2
.e
.read_cr1
.data
32 res
['cr_a'] = sim
.crl
[cr1_sel
].get_range().value
33 cr2_en
= yield dec2
.e
.read_cr2
.ok
36 cr2_sel
= yield dec2
.e
.read_cr2
.data
37 res
['cr_b'] = sim
.crl
[cr2_sel
].get_range().value
38 cr3_en
= yield dec2
.e
.read_cr3
.ok
41 cr3_sel
= yield dec2
.e
.read_cr3
.data
42 res
['cr_c'] = sim
.crl
[cr3_sel
].get_range().value
45 reg1_ok
= yield dec2
.e
.read_reg1
.ok
47 data1
= yield dec2
.e
.read_reg1
.data
48 res
['a'] = sim
.gpr(data1
).value
51 reg2_ok
= yield dec2
.e
.read_reg2
.ok
53 data2
= yield dec2
.e
.read_reg2
.data
54 res
['b'] = sim
.gpr(data2
).value
56 print ("get inputs", res
)
59 def check_cu_outputs(self
, res
, dec2
, sim
, code
):
60 """naming (res) must conform to CRFunctionUnit output regspec
63 print ("check extra output", repr(code
), res
)
66 whole_reg
= yield dec2
.e
.write_cr_whole
67 cr_en
= yield dec2
.e
.write_cr
.ok
69 full_cr
= res
['full_cr']
70 expected_cr
= sim
.cr
.get_range().value
71 print(f
"expected cr {expected_cr:x}, actual: {full_cr:x}")
72 self
.assertEqual(expected_cr
, full_cr
, code
)
76 cr_sel
= yield dec2
.e
.write_cr
.data
77 expected_cr
= sim
.crl
[cr_sel
].get_range().value
79 self
.assertEqual(expected_cr
, real_cr
, code
)
82 out_reg_valid
= yield dec2
.e
.write_reg
.ok
85 write_reg_idx
= yield dec2
.e
.write_reg
.data
86 expected
= sim
.gpr(write_reg_idx
).value
87 print(f
"expected {expected:x}, actual: {alu_out:x}")
88 self
.assertEqual(expected
, alu_out
, code
)
91 if __name__
== "__main__":
92 unittest
.main(exit
=False)
93 suite
= unittest
.TestSuite()
94 suite
.addTest(CRTestRunner(test_data
))
96 runner
= unittest
.TextTestRunner()