cf8572e9be6600f58561bc8568e3a1dac89d493b
[soc.git] / src / soc / fu / compunits / test / test_cr_compunit.py
1 import unittest
2 from soc.decoder.power_enums import (XER_bits, Function)
3
4 # XXX bad practice: use of global variables
5 from soc.fu.cr.test.test_pipe_caller import CRTestCase
6 from soc.fu.cr.test.test_pipe_caller import test_data
7
8 from soc.fu.compunits.compunits import CRFunctionUnit
9 from soc.fu.compunits.test.test_compunit import TestRunner
10
11
12 class CRTestRunner(TestRunner):
13 def __init__(self, test_data):
14 super().__init__(test_data, CRFunctionUnit, self,
15 Function.CR)
16
17 def get_cu_inputs(self, dec2, sim):
18 """naming (res) must conform to CRFunctionUnit input regspec
19 """
20 res = {}
21 full_reg = yield dec2.e.read_cr_whole
22
23 # full CR
24 print(sim.cr.get_range().value)
25 if full_reg:
26 res['full_cr'] = sim.cr.get_range().value
27 else:
28 # CR A
29 cr1_en = yield dec2.e.read_cr1.ok
30 if cr1_en:
31 cr1_sel = yield dec2.e.read_cr1.data
32 res['cr_a'] = sim.crl[cr1_sel].get_range().value
33 cr2_en = yield dec2.e.read_cr2.ok
34 # CR B
35 if cr2_en:
36 cr2_sel = yield dec2.e.read_cr2.data
37 res['cr_b'] = sim.crl[cr2_sel].get_range().value
38 cr3_en = yield dec2.e.read_cr3.ok
39 # CR C
40 if cr3_en:
41 cr3_sel = yield dec2.e.read_cr3.data
42 res['cr_c'] = sim.crl[cr3_sel].get_range().value
43
44 # RA/RC
45 reg1_ok = yield dec2.e.read_reg1.ok
46 if reg1_ok:
47 data1 = yield dec2.e.read_reg1.data
48 res['a'] = sim.gpr(data1).value
49
50 # RB (or immediate)
51 reg2_ok = yield dec2.e.read_reg2.ok
52 if reg2_ok:
53 data2 = yield dec2.e.read_reg2.data
54 res['b'] = sim.gpr(data2).value
55
56 print ("get inputs", res)
57 return res
58
59 def check_cu_outputs(self, res, dec2, sim, code):
60 """naming (res) must conform to CRFunctionUnit output regspec
61 """
62
63 print ("check extra output", repr(code), res)
64
65 # full CR
66 whole_reg = yield dec2.e.write_cr_whole
67 cr_en = yield dec2.e.write_cr.ok
68 if whole_reg:
69 full_cr = res['full_cr']
70 expected_cr = sim.cr.get_range().value
71 print(f"expected cr {expected_cr:x}, actual: {full_cr:x}")
72 self.assertEqual(expected_cr, full_cr, code)
73
74 # part-CR
75 if cr_en:
76 cr_sel = yield dec2.e.write_cr.data
77 expected_cr = sim.crl[cr_sel].get_range().value
78 real_cr = res['cr']
79 self.assertEqual(expected_cr, real_cr, code)
80
81 # RT
82 out_reg_valid = yield dec2.e.write_reg.ok
83 if out_reg_valid:
84 alu_out = res['o']
85 write_reg_idx = yield dec2.e.write_reg.data
86 expected = sim.gpr(write_reg_idx).value
87 print(f"expected {expected:x}, actual: {alu_out:x}")
88 self.assertEqual(expected, alu_out, code)
89
90
91 if __name__ == "__main__":
92 unittest.main(exit=False)
93 suite = unittest.TestSuite()
94 suite.addTest(CRTestRunner(test_data))
95
96 runner = unittest.TextTestRunner()
97 runner.run(suite)