877f14c53813dfedbc7dd891a10ce53d33baa677
2 from soc
.decoder
.power_enums
import (XER_bits
, Function
)
4 from soc
.fu
.logical
.test
.test_pipe_caller
import (LogicalTestCase
,
7 from soc
.fu
.compunits
.compunits
import LogicalFunctionUnit
8 from soc
.fu
.compunits
.test
.test_compunit
import TestRunner
9 from soc
.fu
.test
.common
import ALUHelpers
10 from soc
.config
.endian
import bigendian
13 class LogicalTestRunner(TestRunner
):
14 def __init__(self
, test_data
):
15 super().__init
__(test_data
, LogicalFunctionUnit
, self
,
16 Function
.LOGICAL
, bigendian
)
18 def get_cu_inputs(self
, dec2
, sim
):
19 """naming (res) must conform to LogicalFunctionUnit input regspec
21 res
= yield from get_cu_inputs(dec2
, sim
)
24 def check_cu_outputs(self
, res
, dec2
, sim
, alu
, code
):
25 """naming (res) must conform to LogicalFunctionUnit output regspec
28 rc
= yield dec2
.e
.do
.rc
.data
29 op
= yield dec2
.e
.do
.insn_type
30 cridx_ok
= yield dec2
.e
.write_cr
.ok
31 cridx
= yield dec2
.e
.write_cr
.data
33 print ("check extra output", repr(code
), cridx_ok
, cridx
)
36 self
.assertEqual(cridx_ok
, 1, code
)
37 self
.assertEqual(cridx
, 0, code
)
41 yield from ALUHelpers
.get_sim_int_o(sim_o
, sim
, dec2
)
42 yield from ALUHelpers
.get_wr_sim_cr_a(sim_o
, sim
, dec2
)
44 ALUHelpers
.check_cr_a(self
, res
, sim_o
, "CR%d %s" % (cridx
, code
))
45 ALUHelpers
.check_int_o(self
, res
, sim_o
, code
)
48 if __name__
== "__main__":
49 unittest
.main(exit
=False)
50 suite
= unittest
.TestSuite()
51 suite
.addTest(LogicalTestRunner(LogicalTestCase
.test_data
))
53 runner
= unittest
.TextTestRunner()