big reorg on PowerDecoder2, actually Decode2Execute1Type
[soc.git] / src / soc / fu / compunits / test / test_logical_compunit.py
1 import unittest
2 from soc.decoder.power_enums import (XER_bits, Function)
3
4 from soc.fu.logical.test.test_pipe_caller import LogicalTestCase, get_cu_inputs
5
6 from soc.fu.compunits.compunits import LogicalFunctionUnit
7 from soc.fu.compunits.test.test_compunit import TestRunner
8 from soc.fu.test.common import ALUHelpers
9
10
11 class LogicalTestRunner(TestRunner):
12 def __init__(self, test_data):
13 super().__init__(test_data, LogicalFunctionUnit, self,
14 Function.LOGICAL)
15
16 def get_cu_inputs(self, dec2, sim):
17 """naming (res) must conform to LogicalFunctionUnit input regspec
18 """
19 res = yield from get_cu_inputs(dec2, sim)
20 return res
21
22 def check_cu_outputs(self, res, dec2, sim, code):
23 """naming (res) must conform to LogicalFunctionUnit output regspec
24 """
25
26 rc = yield dec2.e.do.rc.data
27 op = yield dec2.e.do.insn_type
28 cridx_ok = yield dec2.e.write_cr.ok
29 cridx = yield dec2.e.write_cr.data
30
31 print ("check extra output", repr(code), cridx_ok, cridx)
32
33 if rc:
34 self.assertEqual(cridx_ok, 1, code)
35 self.assertEqual(cridx, 0, code)
36
37 sim_o = {}
38
39 yield from ALUHelpers.get_sim_int_o(sim_o, sim, dec2)
40 yield from ALUHelpers.get_wr_sim_cr_a(sim_o, sim, dec2)
41
42 ALUHelpers.check_cr_a(self, res, sim_o, "CR%d %s" % (cridx, code))
43 ALUHelpers.check_int_o(self, res, sim_o, code)
44
45
46 if __name__ == "__main__":
47 unittest.main(exit=False)
48 suite = unittest.TestSuite()
49 suite.addTest(LogicalTestRunner(LogicalTestCase.test_data))
50
51 runner = unittest.TextTestRunner()
52 runner.run(suite)