src/soc/fu/compunits/test/test_shiftrot_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
   6 from soc.fu.shift_rot.test.test_pipe_caller import test_data
   7
   8 from soc.fu.compunits.compunits import ShiftRotFunctionUnit
   9 from soc.fu.compunits.test.test_compunit import TestRunner
  10
  11
  12 class ShiftRotTestRunner(TestRunner):
  13     def __init__(self, test_data):
  14         super().__init__(test_data, ShiftRotFunctionUnit, self,
  15                          Function.SHIFT_ROT)
  16
  17     def get_cu_inputs(self, dec2, sim):
  18         """naming (res) must conform to ShiftRotFunctionUnit input regspec
  19         """
  20         res = {}
  21
  22         # RA
  23         reg1_ok = yield dec2.e.read_reg1.ok
  24         if reg1_ok:
  25             data1 = yield dec2.e.read_reg1.data
  26             res['a'] = sim.gpr(data1).value
  27
  28         # RB
  29         reg2_ok = yield dec2.e.read_reg2.ok
  30         if reg2_ok:
  31             data2 = yield dec2.e.read_reg2.data
  32             res['rb'] = sim.gpr(data2).value
  33
  34         # RS (RC)
  35         reg3_ok = yield dec2.e.read_reg3.ok
  36         if reg3_ok:
  37             data3 = yield dec2.e.read_reg3.data
  38             res['rs'] = sim.gpr(data3).value
  39
  40         # XER.ca
  41         carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  42         carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  43         res['xer_ca'] = carry | (carry32<<1)
  44
  45         print ("inputs", res)
  46
  47         return res
  48
  49     def check_cu_outputs(self, res, dec2, sim, code):
  50         """naming (res) must conform to ShiftRotFunctionUnit output regspec
  51         """
  52
  53         print ("outputs", repr(code), res)
  54
  55         # RT
  56         out_reg_valid = yield dec2.e.write_reg.ok
  57         if out_reg_valid:
  58             write_reg_idx = yield dec2.e.write_reg.data
  59             expected = sim.gpr(write_reg_idx).value
  60             cu_out = res['o']
  61             print(f"expected {expected:x}, actual: {cu_out:x}")
  62             self.assertEqual(expected, cu_out, code)
  63
  64         rc = yield dec2.e.rc.data
  65         op = yield dec2.e.insn_type
  66         cridx_ok = yield dec2.e.write_cr.ok
  67         cridx = yield dec2.e.write_cr.data
  68
  69         print ("check extra output", repr(code), cridx_ok, cridx)
  70
  71         if rc:
  72             self.assertEqual(cridx_ok, 1, code)
  73             self.assertEqual(cridx, 0, code)
  74
  75         # CR (CR0-7)
  76         if cridx_ok:
  77             cr_expected = sim.crl[cridx].get_range().value
  78             cr_actual = res['cr0']
  79             print ("CR", cridx, cr_expected, cr_actual)
  80             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  81
  82         # XER.ca
  83         cry_out = yield dec2.e.output_carry
  84         if cry_out:
  85             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  86             xer_ca = res['xer_ca']
  87             real_carry = xer_ca & 0b1 # XXX CO not CO32
  88             self.assertEqual(expected_carry, real_carry, code)
  89             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  90             real_carry32 = bool(xer_ca & 0b10) # XXX CO32
  91             self.assertEqual(expected_carry32, real_carry32, code)
  92
  93
  94 if __name__ == "__main__":
  95     unittest.main(exit=False)
  96     suite = unittest.TestSuite()
  97     suite.addTest(ShiftRotTestRunner(test_data))
  98
  99     runner = unittest.TextTestRunner()
 100     runner.run(suite)