src/soc/fu/compunits/test/test_shiftrot_compunit.py

   1 import unittest
   2 from soc.decoder.power_enums import (XER_bits, Function)
   3
   4 # XXX bad practice: use of global variables
   5 from soc.fu.shift_rot.test.test_pipe_caller import get_cu_inputs
   6 from soc.fu.shift_rot.test.test_pipe_caller import ShiftRotTestCase
   7 from soc.config.endian import bigendian
   8
   9 from soc.fu.compunits.compunits import ShiftRotFunctionUnit
  10 from soc.fu.compunits.test.test_compunit import TestRunner
  11
  12
  13 class ShiftRotTestRunner(TestRunner):
  14     def __init__(self, test_data):
  15         super().__init__(test_data, ShiftRotFunctionUnit, self,
  16                          Function.SHIFT_ROT, bigendian)
  17
  18     def get_cu_inputs(self, dec2, sim):
  19         """naming (res) must conform to ShiftRotFunctionUnit input regspec
  20         """
  21         res = yield from get_cu_inputs(dec2, sim)
  22         return res
  23
  24     def check_cu_outputs(self, res, dec2, sim, alu, code):
  25         """naming (res) must conform to ShiftRotFunctionUnit output regspec
  26         """
  27
  28         print("outputs", repr(code), res)
  29
  30         # RT
  31         out_reg_valid = yield dec2.e.write_reg.ok
  32         if out_reg_valid:
  33             write_reg_idx = yield dec2.e.write_reg.data
  34             expected = sim.gpr(write_reg_idx).value
  35             cu_out = res['o']
  36             print(f"expected {expected:x}, actual: {cu_out:x}")
  37             self.assertEqual(expected, cu_out, code)
  38
  39         rc = yield dec2.e.do.rc.data
  40         op = yield dec2.e.do.insn_type
  41         cridx_ok = yield dec2.e.write_cr.ok
  42         cridx = yield dec2.e.write_cr.data
  43
  44         print("check extra output", repr(code), cridx_ok, cridx)
  45
  46         if rc:
  47             self.assertEqual(cridx_ok, 1, code)
  48             self.assertEqual(cridx, 0, code)
  49
  50         # CR (CR0-7)
  51         if cridx_ok:
  52             cr_expected = sim.crl[cridx].get_range().value
  53             cr_actual = res['cr_a']
  54             print("CR", cridx, cr_expected, cr_actual)
  55             self.assertEqual(cr_expected, cr_actual, "CR%d %s" % (cridx, code))
  56
  57         # XER.ca
  58         cry_out = yield dec2.e.do.output_carry
  59         if cry_out:
  60             expected_carry = 1 if sim.spr['XER'][XER_bits['CA']] else 0
  61             xer_ca = res['xer_ca']
  62             real_carry = xer_ca & 0b1  # XXX CO not CO32
  63             self.assertEqual(expected_carry, real_carry, code)
  64             expected_carry32 = 1 if sim.spr['XER'][XER_bits['CA32']] else 0
  65             real_carry32 = bool(xer_ca & 0b10)  # XXX CO32
  66             self.assertEqual(expected_carry32, real_carry32, code)
  67
  68
  69 if __name__ == "__main__":
  70     unittest.main(exit=False)
  71     suite = unittest.TestSuite()
  72     suite.addTest(ShiftRotTestRunner(ShiftRotTestCase.test_data))
  73
  74     runner = unittest.TextTestRunner()
  75     runner.run(suite)